rtl-simulation

Here are 6 public repositories matching this topic...

sincerelystepper / renode-verilator-integration-windows

Agrionics Co.'s open source simulation and windows virtual development for intricate embedded developers

windows fpga embedded-systems msys2 systemverilog verilator co-simulation hardware-verification renode virtual-platform soc-verification rtl-simulation

Updated Jun 15, 2026
C++

lanserge / cxxrtl-vpi

Sponsor

Star

An IEEE-1364 VPI interface for CXXRTL (the Yosys C++ simulation backend), so cocotb can drive CXXRTL models.

python simulator verilog systemverilog yosys vpi cocotb hardware-verification cxxrtl rtl-simulation

Updated Jun 24, 2026
C++

Design and implementation of an ASIC with an 8051 microcontroller core. Includes VHDL modules, C applications, RTL simulations, and mixed-signal validation. Focused on hardware-software co-design and optimization.

vhdl embedded-systems logic-synthesis 8051-architecture asic-design hardware-software-co-design microcontroller-integration rtl-simulation mixed-signal-simulation digital-circuit-optimization

Updated Jan 8, 2025
VHDL

Kannan-7814 / 4bit_PRNG

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This project implements a 4-bit pseudo-random number generator (PRNG) on the Basys 3 FPGA board using Verilog. The PRNG is designed using a Linear Feedback Shift Register (LFSR) with a tapped XOR feedback mechanism.

verilog verilog-hdl pseudorandom simualtion verilog-project fpga-programming basys3-fpga rtl-design prng-algorithms rtl-simulation