diff --git a/arch/riscv/dts/eic7700-hifive-premier-p550.dts b/arch/riscv/dts/eic7700-hifive-premier-p550.dts
index a08af6cf6c0..d82cd6d3b45 100644
--- a/arch/riscv/dts/eic7700-hifive-premier-p550.dts
+++ b/arch/riscv/dts/eic7700-hifive-premier-p550.dts
@@ -155,6 +155,12 @@
 &uart0 {
 	status = "okay";
 };
+/delete-node/ &d1_pmp;
+/delete-node/ &d1_mbox_srvc;
+/delete-node/ &d1_mbox;
+/delete-node/ &d1_mbox_srvc1;
+/delete-node/ &d1_mbox1;
+/delete-node/ &plic1;
 
 &bootspi {
 	status = "okay";
diff --git a/arch/riscv/dts/eic770x.dtsi b/arch/riscv/dts/eic770x.dtsi
index ec8d3649c66..612a48a416a 100644
--- a/arch/riscv/dts/eic770x.dtsi
+++ b/arch/riscv/dts/eic770x.dtsi
@@ -33,6 +33,7 @@
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
+		timebase-frequency = <1000000>;
 		cpu0: cpu@0 {
 			clock-frequency = <0>;
 			compatible = "eic7700", "riscv";
@@ -48,6 +49,7 @@
 			i-tlb-sets = <1>;
 			i-tlb-size = <64>;
 			mmu-type = "riscv,sv48";
+			next-level-cache = <&l2_cache_0>;
 			reg = <0>;
 			riscv,isa = "rv64imafdc_zba_zbb";
 			status = "disabled";
@@ -74,6 +76,7 @@
 			i-tlb-sets = <1>;
 			i-tlb-size = <64>;
 			mmu-type = "riscv,sv48";
+			next-level-cache = <&l2_cache_1>;
 			reg = <0x1>;
 			riscv,isa = "rv64imafdc_zba_zbb";
 			status = "disabled";
@@ -100,6 +103,7 @@
 			i-tlb-sets = <1>;
 			i-tlb-size = <64>;
 			mmu-type = "riscv,sv48";
+			next-level-cache = <&l2_cache_2>;
 			reg = <0x2>;
 			riscv,isa = "rv64imafdc_zba_zbb";
 			status = "disabled";
@@ -126,6 +130,7 @@
 			i-tlb-sets = <1>;
 			i-tlb-size = <64>;
 			mmu-type = "riscv,sv48";
+			next-level-cache = <&l2_cache_3>;
 			reg = <0x3>;
 			riscv,isa = "rv64imafdc_zba_zbb";
 			status = "disabled";
@@ -152,6 +157,7 @@
 			i-tlb-sets = <1>;
 			i-tlb-size = <64>;
 			mmu-type = "riscv,sv48";
+			//next-level-cache = <&l2_cache_4>;
 			reg = <0x4>;
 			riscv,isa = "rv64imafdc_zba_zbb";
 			status = "disabled";
@@ -178,6 +184,7 @@
 			i-tlb-sets = <1>;
 			i-tlb-size = <64>;
 			mmu-type = "riscv,sv48";
+			//next-level-cache = <&l2_cache_5>;
 			reg = <0x5>;
 			riscv,isa = "rv64imafdc_zba_zbb";
 			status = "disabled";
@@ -204,6 +211,7 @@
 			i-tlb-sets = <1>;
 			i-tlb-size = <64>;
 			mmu-type = "riscv,sv48";
+			//next-level-cache = <&l2_cache_6>;
 			reg = <0x6>;
 			riscv,isa = "rv64imafdc_zba_zbb";
 			status = "disabled";
@@ -230,6 +238,7 @@
 			i-tlb-sets = <1>;
 			i-tlb-size = <64>;
 			mmu-type = "riscv,sv48";
+			//next-level-cache = <&l2_cache_7>;
 			reg = <0x7>;
 			riscv,isa = "rv64imafdc_zba_zbb";
 			status = "disabled";
@@ -304,6 +313,65 @@
 		#size-cells = <2>;
 		compatible = "ESWIN,EIC7700-soc", "eic7700-soc", "eswin-soc";
 		ranges;
+		l2_cache_0: pl2@104000 {
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-sets = <512>;
+			cache-size = <262144>;
+			cache-unified;
+			compatible = "sifive,pl2cache1", "cache";
+			next-level-cache = <&ccache>;
+			reg = <0x0 0x104000 0x0 0x4000>;
+			sifive,perfmon-counters = <6>;
+		};
+
+		l2_cache_1: pl2@108000 {
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-sets = <512>;
+			cache-size = <262144>;
+			cache-unified;
+			compatible = "sifive,pl2cache1", "cache";
+			next-level-cache = <&ccache>;
+			reg = <0x0 0x108000 0x0 0x4000>;
+			sifive,perfmon-counters = <6>;
+		};
+
+		l2_cache_2: pl2@10c000 {
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-sets = <512>;
+			cache-size = <262144>;
+			cache-unified;
+			compatible = "sifive,pl2cache1", "cache";
+			next-level-cache = <&ccache>;
+			reg = <0x0 0x10c000 0x0 0x4000>;
+			sifive,perfmon-counters = <6>;
+		};
+
+		l2_cache_3: pl2@110000 {
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-sets = <512>;
+			cache-size = <262144>;
+			cache-unified;
+			compatible = "sifive,pl2cache1", "cache";
+			next-level-cache = <&ccache>;
+			reg = <0x0 0x110000 0x0 0x4000>;
+			sifive,perfmon-counters = <6>;
+		};
+
+		ccache: cache-controller@2010000 {
+			compatible = "sifive,ccache2";
+			cache-block-size = <64>;
+			cache-level = <3>;
+			cache-sets = <4096>;
+			cache-size = <4194304>;
+			cache-unified;
+			interrupts = <1>, <3>, <4>, <2>;
+			reg = <0x0 0x2010000 0x0 0x4000>;
+		};
+
 		d0_mbox: mbox@0x50a00000 {
 			status = "disabled";
 			compatible = "eswin,mbox";
@@ -495,6 +563,16 @@
 			};
 		#endif
 		};
+		clint: timer@2000000 {
+			compatible = "eswin,eic7700-clint", "sifive,clint0";
+			reg = <0x0 0x02000000 0x0 0x10000>;
+			interrupts-extended =
+				<&cpu0_intc 3>, <&cpu0_intc 7>,
+				<&cpu1_intc 3>, <&cpu1_intc 7>,
+				<&cpu2_intc 3>, <&cpu2_intc 7>,
+				<&cpu3_intc 3>, <&cpu3_intc 7>;
+		};
+
 		plic0: interrupt-controller@c000000 {
 			status = "disabled";
 			#interrupt-cells = <1>;
@@ -594,15 +672,19 @@
 		};
 		uart0: serial@50900000 {
 			status = "disabled";
-			compatible = "synopsys,uart0";
+			compatible = "snps,dw-apb-uart";
 			clock-frequency = <200000000>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
 			reg = <0x0 0x50900000 0x0 0xffff>;
 			reg-names = "control";
 		};
 		uart1: serial@50910000 {
 			status = "disabled";
-			compatible = "synopsys,uart0";
+			compatible = "snps,dw-apb-uart";
 			clock-frequency = <200000000>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
 			reg = <0x0 0x50910000 0x0 0xffff>;
 			reg-names = "control";
 		};
diff --git a/configs/hifive_premier_p550_defconfig b/configs/hifive_premier_p550_defconfig
index f71c7c838bf..328e195c392 100644
--- a/configs/hifive_premier_p550_defconfig
+++ b/configs/hifive_premier_p550_defconfig
@@ -94,7 +94,7 @@ CONFIG_PCIE_DW_ESWIN=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_RESET_ESWIN=y
-CONFIG_ESWIN_UART_SYNOPSYS=y
+CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DESIGNWARE_SPI=y
 CONFIG_ESWIN_SPI=y