diff --git a/library/SubcircuitLibrary/CD4016/CD4016.cir b/library/SubcircuitLibrary/CD4016/CD4016.cir new file mode 100644 index 000000000..4f7ec7687 --- /dev/null +++ b/library/SubcircuitLibrary/CD4016/CD4016.cir @@ -0,0 +1,27 @@ +.title KiCad schematic +R6 Gnd SIGD_IN 1000k +U1 SIGA_IN SIGA_OUT SIGB_IN SIGB_OUT B C Gnd SIGC_IN SIGC_OUT SIGD_OUT SIGD_IN D A vdd PORT +R8 Gnd SIGD_OUT 1000k +M15 SIGD_OUT Net-_M11-Pad1_ SIGD_IN vdd eSim_MOS_P +M16 SIGD_OUT D SIGD_IN Gnd eSim_MOS_N +M11 Net-_M11-Pad1_ D Gnd Gnd eSim_MOS_N +M12 Net-_M11-Pad1_ D vdd vdd eSim_MOS_P +M9 Net-_M10-Pad1_ B Gnd Gnd eSim_MOS_N +M10 Net-_M10-Pad1_ B vdd vdd eSim_MOS_P +R5 Gnd SIGB_IN 1000k +M13 SIGB_OUT Net-_M10-Pad1_ SIGB_IN vdd eSim_MOS_P +M14 SIGB_OUT B SIGB_IN Gnd eSim_MOS_N +R7 Gnd SIGB_OUT 1000k +R3 Gnd SIGA_OUT 1000k +M6 SIGC_OUT Net-_M3-Pad1_ SIGC_IN vdd eSim_MOS_P +R4 Gnd SIGC_OUT 1000k +R2 Gnd SIGC_IN 1000k +M8 SIGC_OUT C SIGC_IN Gnd eSim_MOS_N +M4 Net-_M3-Pad1_ C vdd vdd eSim_MOS_P +M2 Net-_M1-Pad1_ A vdd vdd eSim_MOS_P +M7 SIGA_OUT A SIGA_IN Gnd eSim_MOS_N +M5 SIGA_OUT Net-_M1-Pad1_ SIGA_IN vdd eSim_MOS_P +M3 Net-_M3-Pad1_ C Gnd Gnd eSim_MOS_N +M1 Net-_M1-Pad1_ A Gnd Gnd eSim_MOS_N +R1 Gnd SIGA_IN 1000k +.end diff --git a/library/SubcircuitLibrary/CD4016/CD4016.cir.out b/library/SubcircuitLibrary/CD4016/CD4016.cir.out new file mode 100644 index 000000000..1f677e9e1 --- /dev/null +++ b/library/SubcircuitLibrary/CD4016/CD4016.cir.out @@ -0,0 +1,38 @@ +.title kicad schematic + +.include PMOS-180nm.lib +.include NMOS-180nm.lib +r6 gnd sigd_in 1000k +* u1 siga_in siga_out sigb_in sigb_out b c gnd sigc_in sigc_out sigd_out sigd_in d a vdd port +r8 gnd sigd_out 1000k +m15 sigd_out net-_m11-pad1_ sigd_in vdd CMOSP W=100u L=0.18u M=1 +m16 sigd_out d sigd_in gnd CMOSN W=100u L=0.18u M=1 +m11 net-_m11-pad1_ d gnd gnd CMOSN W=0.36u L=0.18u M=1 +m12 net-_m11-pad1_ d vdd vdd CMOSP W=0.72u L=0.18u M=1 +m9 net-_m10-pad1_ b gnd gnd CMOSN W=0.36u L=0.18u M=1 +m10 net-_m10-pad1_ b vdd vdd CMOSP W=0.72u L=0.18u M=1 +r5 gnd sigb_in 1000k +m13 sigb_out net-_m10-pad1_ sigb_in vdd CMOSP W=100u L=0.18u M=1 +m14 sigb_out b sigb_in gnd CMOSN W=100u L=0.18u M=1 +r7 gnd sigb_out 1000k +r3 gnd siga_out 1000k +m6 sigc_out net-_m3-pad1_ sigc_in vdd CMOSP W=100u L=0.18u M=1 +r4 gnd sigc_out 1000k +r2 gnd sigc_in 1000k +m8 sigc_out c sigc_in gnd CMOSN W=100u L=0.18u M=1 +m4 net-_m3-pad1_ c vdd vdd CMOSP W=100u L=0.18u M=1 +m2 net-_m1-pad1_ a vdd vdd CMOSP W=0.72u L=0.18u M=1 +m7 siga_out a siga_in gnd CMOSN W=100u L=0.18u M=1 +m5 siga_out net-_m1-pad1_ siga_in vdd CMOSP W=100u L=0.18u M=1 +m3 net-_m3-pad1_ c gnd gnd CMOSN W=100u L=0.18u M=1 +m1 net-_m1-pad1_ a gnd gnd CMOSN W=0.36u L=0.18u M=1 +r1 gnd siga_in 1000k +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4016/CD4016.kicad_sch b/library/SubcircuitLibrary/CD4016/CD4016.kicad_sch new file mode 100644 index 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1.27)))) + ) + (pin input line (at -3.81 -6.35 90) (length 5.08) + (name "~" (effects (font (size 1.27 1.27)))) + (number "2" (effects (font (size 1.27 1.27)))) + ) + (pin input line (at 8.89 0 180) (length 5.08) + (name "~" (effects (font (size 1.27 1.27)))) + (number "3" (effects (font (size 1.27 1.27)))) + ) + (pin output line (at 3.81 -6.35 90) (length 5.08) + (name "~" (effects (font (size 1.27 1.27)))) + (number "4" (effects (font (size 1.27 1.27)))) + ) + ) + ) +) diff --git a/library/SubcircuitLibrary/CD4016/CD4016.sub b/library/SubcircuitLibrary/CD4016/CD4016.sub new file mode 100644 index 000000000..c8de3175a --- /dev/null +++ b/library/SubcircuitLibrary/CD4016/CD4016.sub @@ -0,0 +1,32 @@ +* Subcircuit CD4016 +.subckt CD4016 siga_in siga_out sigb_in sigb_out b c gnd sigc_in sigc_out sigd_out sigd_in d a vdd +.title kicad schematic +.include PMOS-180nm.lib +.include NMOS-180nm.lib +r6 gnd sigd_in 1000k +r8 gnd sigd_out 1000k +m15 sigd_out net-_m11-pad1_ sigd_in vdd CMOSP W=100u L=0.18u M=1 +m16 sigd_out d sigd_in gnd CMOSN W=100u L=0.18u M=1 +m11 net-_m11-pad1_ d gnd gnd CMOSN W=0.36u L=0.18u M=1 +m12 net-_m11-pad1_ d vdd vdd CMOSP W=0.72u L=0.18u M=1 +m9 net-_m10-pad1_ b gnd gnd CMOSN W=0.36u L=0.18u M=1 +m10 net-_m10-pad1_ b vdd vdd CMOSP W=0.72u L=0.18u M=1 +r5 gnd sigb_in 1000k +m13 sigb_out net-_m10-pad1_ sigb_in vdd CMOSP W=100u L=0.18u M=1 +m14 sigb_out b sigb_in gnd CMOSN W=100u L=0.18u M=1 +r7 gnd sigb_out 1000k +r3 gnd siga_out 1000k +m6 sigc_out net-_m3-pad1_ sigc_in vdd CMOSP W=100u L=0.18u M=1 +r4 gnd sigc_out 1000k +r2 gnd sigc_in 1000k +m8 sigc_out c sigc_in gnd CMOSN W=100u L=0.18u M=1 +m4 net-_m3-pad1_ c vdd vdd CMOSP W=100u L=0.18u M=1 +m2 net-_m1-pad1_ a vdd vdd CMOSP W=0.72u L=0.18u M=1 +m7 siga_out a siga_in gnd CMOSN W=100u L=0.18u M=1 +m5 siga_out net-_m1-pad1_ siga_in vdd CMOSP W=100u L=0.18u M=1 +m3 net-_m3-pad1_ c gnd gnd CMOSN W=100u L=0.18u M=1 +m1 net-_m1-pad1_ a gnd gnd CMOSN W=0.36u L=0.18u M=1 +r1 gnd siga_in 1000k +* Control Statements + +.ends CD4016 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4016/CD4016_Previous_Values.xml b/library/SubcircuitLibrary/CD4016/CD4016_Previous_Values.xml new file mode 100644 index 000000000..58108db9b --- /dev/null +++ b/library/SubcircuitLibrary/CD4016/CD4016_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib2u0.18uC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib1u0.18uC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib0.36u0.18uC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib0.72u0.18uC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib0.36u0.18uC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib0.72u0.18uC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib2u0.18uC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib1u0.18uC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib2u0.18uC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib1u0.18uC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib0.72u0.18uC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib0.72u0.18uC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib1u0.18uC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib2u0.18uC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib0.36u0.18uC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib0.36u0.18utruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4016/NMOS-180nm.lib b/library/SubcircuitLibrary/CD4016/NMOS-180nm.lib new file mode 100644 index 000000000..51e9b1196 --- /dev/null +++ b/library/SubcircuitLibrary/CD4016/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/CD4016/PMOS-180nm.lib b/library/SubcircuitLibrary/CD4016/PMOS-180nm.lib new file mode 100644 index 000000000..032b5b95e --- /dev/null +++ b/library/SubcircuitLibrary/CD4016/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/CD4016/analysis b/library/SubcircuitLibrary/CD4016/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/CD4016/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4026B/CD4026B.cir b/library/SubcircuitLibrary/CD4026B/CD4026B.cir new file mode 100644 index 000000000..ed932371b --- /dev/null +++ b/library/SubcircuitLibrary/CD4026B/CD4026B.cir @@ -0,0 +1,61 @@ +.title KiCad schematic +U7 Net-_U13-Pad2_ Net-_U15-Pad2_ Net-_U11-Pad2_ d_and +U9 Net-_U15-Pad1_ Net-_U10-Pad5_ Net-_U11-Pad1_ d_and +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_or +U20 Net-_U17-Pad1_ Net-_U12-Pad5_ Net-_U20-Pad3_ d_or +U21 Net-_U10-Pad1_ Net-_U10-Pad6_ Net-_U21-Pad3_ d_or +U12 Net-_U10-Pad5_ Net-_U10-Pad2_ Net-_U1-Pad2_ RESET_dig Net-_U12-Pad5_ Net-_U12-Pad6_ d_dff +U8 Net-_U15-Pad1_ Net-_U10-Pad2_ Net-_U1-Pad2_ RESET_dig Net-_U10-Pad1_ Net-_U13-Pad2_ d_dff +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U1-Pad2_ RESET_dig Net-_U10-Pad5_ Net-_U10-Pad6_ d_dff +U2 CLK_dig CLK_Inhibit_dig DisplayEnableIn_Dig DisplayEnableIn_Dig Net-_U2-Pad5_ Net-_U2-Pad6_ Net-_U2-Pad7_ unconnected-_U2-Pad8_ Net-_U2-Pad9_ Net-_U2-Pad10_ Net-_U2-Pad11_ Net-_U2-Pad12_ Net-_U2-Pad13_ Net-_U18-Pad3_ RESET_dig unconnected-_U2-Pad16_ PORT +U1 GND Net-_U1-Pad2_ adc_bridge_1 +U3 CLK_Inhibit_dig Net-_U3-Pad2_ d_inverter +U5 Net-_U12-Pad6_ Net-_U10-Pad2_ Net-_U1-Pad2_ RESET_dig Net-_U17-Pad1_ Net-_U15-Pad2_ d_dff +U6 Net-_U17-Pad1_ Net-_U10-Pad2_ Net-_U1-Pad2_ RESET_dig Net-_U15-Pad1_ Net-_U17-Pad2_ d_dff +U4 CLK_dig Net-_U3-Pad2_ Net-_U10-Pad2_ d_and +U22 Net-_U13-Pad2_ Net-_U10-Pad5_ unconnected-_U22-Pad3_ d_or +U13 Net-_U12-Pad5_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_and +U14 Net-_U10-Pad6_ Net-_U12-Pad5_ Net-_U14-Pad3_ d_or +U19 Net-_U15-Pad1_ Net-_U13-Pad2_ Net-_U19-Pad3_ d_or +U16 Net-_U15-Pad2_ Net-_U12-Pad6_ Net-_U16-Pad3_ d_or +U18 Net-_U17-Pad2_ Net-_U10-Pad1_ Net-_U18-Pad3_ d_or +U17 Net-_U17-Pad1_ Net-_U17-Pad2_ Net-_U17-Pad3_ d_or +U15 Net-_U15-Pad1_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_or +U37 Net-_U30-Pad3_ Net-_U18-Pad3_ Net-_U37-Pad3_ d_and +U29 Net-_U19-Pad3_ Net-_U14-Pad3_ Net-_U29-Pad3_ d_and +U36 Net-_U29-Pad3_ Net-_U15-Pad3_ Net-_U36-Pad3_ d_and +U30 Net-_U20-Pad3_ Net-_U17-Pad3_ Net-_U30-Pad3_ d_and +U33 Net-_U18-Pad3_ DisplayEnableIn_Dig Net-_U2-Pad13_ d_and +U32 Net-_U24-Pad3_ DisplayEnableIn_Dig Net-_U2-Pad12_ d_and +U38 Net-_U36-Pad3_ DisplayEnableIn_Dig Net-_U2-Pad9_ d_and +U24 Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U24-Pad3_ d_and +U26 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U26-Pad3_ d_and +U25 Net-_U2-Pad5_ Cout dac_bridge_1 +U31 Net-_U26-Pad3_ DisplayEnableIn_Dig Net-_U2-Pad10_ d_and +U23 Net-_U12-Pad5_ Net-_U2-Pad5_ d_inverter +U27 Cout plot_v1 +U56 d plot_v1 +U52 ungated_c plot_v1 +U53 a plot_v1 +U55 b plot_v1 +U54 c plot_v1 +U59 e plot_v1 +U35 Net-_U13-Pad3_ Net-_U15-Pad1_ Net-_U35-Pad3_ d_or +U28 DisplayEnableIn_Dig DisplayEnableOut dac_bridge_1 +U34 DisplayEnableOut plot_v1 +U40 Net-_U35-Pad3_ DisplayEnableIn_Dig Net-_U2-Pad7_ d_and +U39 Net-_U37-Pad3_ Net-_U21-Pad3_ Net-_U39-Pad3_ d_and +U41 Net-_U39-Pad3_ DisplayEnableIn_Dig Net-_U41-Pad3_ d_and +U42 Net-_U11-Pad3_ DisplayEnableIn_Dig Net-_U2-Pad6_ d_and +U47 Net-_U2-Pad12_ b dac_bridge_1 +U46 Net-_U2-Pad10_ a dac_bridge_1 +U45 Net-_U2-Pad9_ d dac_bridge_1 +U48 Net-_U2-Pad13_ c dac_bridge_1 +U44 Net-_U18-Pad3_ ungated_c dac_bridge_1 +U50 Net-_U2-Pad7_ g dac_bridge_1 +U49 Net-_U2-Pad6_ f dac_bridge_1 +U43 Net-_U41-Pad3_ Net-_U2-Pad11_ d_inverter +U51 Net-_U2-Pad11_ e dac_bridge_1 +U58 g plot_v1 +U57 f plot_v1 +.end diff --git a/library/SubcircuitLibrary/CD4026B/CD4026B.cir.out b/library/SubcircuitLibrary/CD4026B/CD4026B.cir.out new file mode 100644 index 000000000..ab934e1b0 --- /dev/null +++ b/library/SubcircuitLibrary/CD4026B/CD4026B.cir.out @@ -0,0 +1,224 @@ +.title kicad schematic + +* u7 net-_u13-pad2_ net-_u15-pad2_ net-_u11-pad2_ d_and +* u9 net-_u15-pad1_ net-_u10-pad5_ net-_u11-pad1_ d_and +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_or +* u20 net-_u17-pad1_ net-_u12-pad5_ net-_u20-pad3_ d_or +* u21 net-_u10-pad1_ net-_u10-pad6_ net-_u21-pad3_ d_or +* u12 net-_u10-pad5_ net-_u10-pad2_ net-_u1-pad2_ reset_dig net-_u12-pad5_ net-_u12-pad6_ d_dff +* u8 net-_u15-pad1_ net-_u10-pad2_ net-_u1-pad2_ reset_dig net-_u10-pad1_ net-_u13-pad2_ d_dff +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad2_ reset_dig net-_u10-pad5_ net-_u10-pad6_ d_dff +* u2 clk_dig clk_inhibit_dig displayenablein_dig displayenablein_dig net-_u2-pad5_ net-_u2-pad6_ net-_u2-pad7_ unconnected-_u2-pad8_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u18-pad3_ reset_dig unconnected-_u2-pad16_ port +* u1 gnd net-_u1-pad2_ adc_bridge_1 +* u3 clk_inhibit_dig net-_u3-pad2_ d_inverter +* u5 net-_u12-pad6_ net-_u10-pad2_ net-_u1-pad2_ reset_dig net-_u17-pad1_ net-_u15-pad2_ d_dff +* u6 net-_u17-pad1_ net-_u10-pad2_ net-_u1-pad2_ reset_dig net-_u15-pad1_ net-_u17-pad2_ d_dff +* u4 clk_dig net-_u3-pad2_ net-_u10-pad2_ d_and +* u22 net-_u13-pad2_ net-_u10-pad5_ unconnected-_u22-pad3_ d_or +* u13 net-_u12-pad5_ net-_u13-pad2_ net-_u13-pad3_ d_and +* u14 net-_u10-pad6_ net-_u12-pad5_ net-_u14-pad3_ d_or +* u19 net-_u15-pad1_ net-_u13-pad2_ net-_u19-pad3_ d_or +* u16 net-_u15-pad2_ net-_u12-pad6_ net-_u16-pad3_ d_or +* u18 net-_u17-pad2_ net-_u10-pad1_ net-_u18-pad3_ d_or +* u17 net-_u17-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_or +* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_or +* u37 net-_u30-pad3_ net-_u18-pad3_ net-_u37-pad3_ d_and +* u29 net-_u19-pad3_ net-_u14-pad3_ net-_u29-pad3_ d_and +* u36 net-_u29-pad3_ net-_u15-pad3_ net-_u36-pad3_ d_and +* u30 net-_u20-pad3_ net-_u17-pad3_ net-_u30-pad3_ d_and +* u33 net-_u18-pad3_ displayenablein_dig net-_u2-pad13_ d_and +* u32 net-_u24-pad3_ displayenablein_dig net-_u2-pad12_ d_and +* u38 net-_u36-pad3_ displayenablein_dig net-_u2-pad9_ d_and +* u24 net-_u16-pad3_ net-_u17-pad3_ net-_u24-pad3_ d_and +* u26 net-_u14-pad3_ net-_u15-pad3_ net-_u26-pad3_ d_and +* u25 net-_u2-pad5_ cout dac_bridge_1 +* u31 net-_u26-pad3_ displayenablein_dig net-_u2-pad10_ d_and +* u23 net-_u12-pad5_ net-_u2-pad5_ d_inverter +* u27 cout plot_v1 +* u56 d plot_v1 +* u52 ungated_c plot_v1 +* u53 a plot_v1 +* u55 b plot_v1 +* u54 c plot_v1 +* u59 e plot_v1 +* u35 net-_u13-pad3_ net-_u15-pad1_ net-_u35-pad3_ d_or +* u28 displayenablein_dig displayenableout dac_bridge_1 +* u34 displayenableout plot_v1 +* u40 net-_u35-pad3_ displayenablein_dig net-_u2-pad7_ d_and +* u39 net-_u37-pad3_ net-_u21-pad3_ net-_u39-pad3_ d_and +* u41 net-_u39-pad3_ displayenablein_dig net-_u41-pad3_ d_and +* u42 net-_u11-pad3_ displayenablein_dig net-_u2-pad6_ d_and +* u47 net-_u2-pad12_ b dac_bridge_1 +* u46 net-_u2-pad10_ a dac_bridge_1 +* u45 net-_u2-pad9_ d dac_bridge_1 +* u48 net-_u2-pad13_ c dac_bridge_1 +* u44 net-_u18-pad3_ ungated_c dac_bridge_1 +* u50 net-_u2-pad7_ g dac_bridge_1 +* u49 net-_u2-pad6_ f dac_bridge_1 +* u43 net-_u41-pad3_ net-_u2-pad11_ d_inverter +* u51 net-_u2-pad11_ e dac_bridge_1 +* u58 g plot_v1 +* u57 f plot_v1 +a1 [net-_u13-pad2_ net-_u15-pad2_ ] net-_u11-pad2_ u7 +a2 [net-_u15-pad1_ net-_u10-pad5_ ] net-_u11-pad1_ u9 +a3 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a4 [net-_u17-pad1_ net-_u12-pad5_ ] net-_u20-pad3_ u20 +a5 [net-_u10-pad1_ net-_u10-pad6_ ] net-_u21-pad3_ u21 +a6 net-_u10-pad5_ net-_u10-pad2_ net-_u1-pad2_ reset_dig net-_u12-pad5_ net-_u12-pad6_ u12 +a7 net-_u15-pad1_ net-_u10-pad2_ net-_u1-pad2_ reset_dig net-_u10-pad1_ net-_u13-pad2_ u8 +a8 net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad2_ reset_dig net-_u10-pad5_ net-_u10-pad6_ u10 +a9 [gnd ] [net-_u1-pad2_ ] u1 +a10 clk_inhibit_dig net-_u3-pad2_ u3 +a11 net-_u12-pad6_ net-_u10-pad2_ net-_u1-pad2_ reset_dig net-_u17-pad1_ net-_u15-pad2_ u5 +a12 net-_u17-pad1_ net-_u10-pad2_ net-_u1-pad2_ reset_dig net-_u15-pad1_ net-_u17-pad2_ u6 +a13 [clk_dig net-_u3-pad2_ ] net-_u10-pad2_ u4 +a14 [net-_u13-pad2_ net-_u10-pad5_ ] unconnected-_u22-pad3_ u22 +a15 [net-_u12-pad5_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a16 [net-_u10-pad6_ net-_u12-pad5_ ] net-_u14-pad3_ u14 +a17 [net-_u15-pad1_ net-_u13-pad2_ ] net-_u19-pad3_ u19 +a18 [net-_u15-pad2_ net-_u12-pad6_ ] net-_u16-pad3_ u16 +a19 [net-_u17-pad2_ net-_u10-pad1_ ] net-_u18-pad3_ u18 +a20 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17 +a21 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a22 [net-_u30-pad3_ net-_u18-pad3_ ] net-_u37-pad3_ u37 +a23 [net-_u19-pad3_ net-_u14-pad3_ ] net-_u29-pad3_ u29 +a24 [net-_u29-pad3_ net-_u15-pad3_ ] net-_u36-pad3_ u36 +a25 [net-_u20-pad3_ net-_u17-pad3_ ] net-_u30-pad3_ u30 +a26 [net-_u18-pad3_ displayenablein_dig ] net-_u2-pad13_ u33 +a27 [net-_u24-pad3_ displayenablein_dig ] net-_u2-pad12_ u32 +a28 [net-_u36-pad3_ displayenablein_dig ] net-_u2-pad9_ u38 +a29 [net-_u16-pad3_ net-_u17-pad3_ ] net-_u24-pad3_ u24 +a30 [net-_u14-pad3_ net-_u15-pad3_ ] net-_u26-pad3_ u26 +a31 [net-_u2-pad5_ ] [cout ] u25 +a32 [net-_u26-pad3_ displayenablein_dig ] net-_u2-pad10_ u31 +a33 net-_u12-pad5_ net-_u2-pad5_ u23 +a34 [net-_u13-pad3_ net-_u15-pad1_ ] net-_u35-pad3_ u35 +a35 [displayenablein_dig ] [displayenableout ] u28 +a36 [net-_u35-pad3_ displayenablein_dig ] net-_u2-pad7_ u40 +a37 [net-_u37-pad3_ net-_u21-pad3_ ] net-_u39-pad3_ u39 +a38 [net-_u39-pad3_ displayenablein_dig ] net-_u41-pad3_ u41 +a39 [net-_u11-pad3_ displayenablein_dig ] net-_u2-pad6_ u42 +a40 [net-_u2-pad12_ ] [b ] u47 +a41 [net-_u2-pad10_ ] [a ] u46 +a42 [net-_u2-pad9_ ] [d ] u45 +a43 [net-_u2-pad13_ ] [c ] u48 +a44 [net-_u18-pad3_ ] [ungated_c ] u44 +a45 [net-_u2-pad7_ ] [g ] u50 +a46 [net-_u2-pad6_ ] [f ] u49 +a47 net-_u41-pad3_ net-_u2-pad11_ u43 +a48 [net-_u2-pad11_ ] [e ] u51 +* Schematic Name: d_and, Ngspice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u11 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u20 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u21 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u12 d_dff(clk_delay=1.0e-12 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-12 fall_delay=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u8 d_dff(clk_delay=1.0e-12 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-12 fall_delay=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u10 d_dff(clk_delay=1.0e-12 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-12 fall_delay=1.0e-12 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u1 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u5 d_dff(clk_delay=1.0e-12 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-12 fall_delay=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u6 d_dff(clk_delay=1.0e-12 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-12 fall_delay=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u22 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u14 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u19 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u16 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u18 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u15 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u37 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u25 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u35 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u28 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u40 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u39 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u41 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u42 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u47 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u46 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u45 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u48 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u44 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u50 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u49 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u51 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(cout) +plot v(d) +plot v(ungated_c) +plot v(a) +plot v(b) +plot v(c) +plot v(e) +plot v(displayenableout) +plot v(g) +plot v(f) +.endc +.end diff --git a/library/SubcircuitLibrary/CD4026B/CD4026B.kicad_sch b/library/SubcircuitLibrary/CD4026B/CD4026B.kicad_sch new file mode 100644 index 000000000..05f536c7a --- /dev/null +++ b/library/SubcircuitLibrary/CD4026B/CD4026B.kicad_sch @@ -0,0 +1,3942 @@ +(kicad_sch (version 20211123) (generator eeschema) + + (uuid 8a741bac-eee8-4878-ab44-c9b9867a0e4f) + + (paper "A4") + + (lib_symbols + (symbol "eSim_Digital:d_and" (pin_names (offset 1.016)) (in_bom yes) (on_board yes) + (property "Reference" "U" (id 0) (at 0 0 0) + (effects (font (size 1.524 1.524))) + ) + (property "Value" "d_and" (id 1) (at 1.27 2.54 0) + (effects (font (size 1.524 1.524))) + ) + (property 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+ ) + (path "/cce0457d-fe4d-4a15-a924-f12d279cf253" + (reference "U44") (unit 1) (value "dac_bridge_1") (footprint "") + ) + (path "/546506a4-1c8d-40fe-baa6-c2deef6ded76" + (reference "U45") (unit 1) (value "dac_bridge_1") (footprint "") + ) + (path "/79e143e8-81b1-422e-86dc-ddbe64682338" + (reference "U46") (unit 1) (value "dac_bridge_1") (footprint "") + ) + (path "/5ba7d315-21dc-4b35-b568-0faa004fe024" + (reference "U47") (unit 1) (value "dac_bridge_1") (footprint "") + ) + (path "/b69e5767-dca8-4015-a5c6-1c6735138972" + (reference "U48") (unit 1) (value "dac_bridge_1") (footprint "") + ) + (path "/341dde18-2010-41d5-9b4b-650dc3e89c61" + (reference "U49") (unit 1) (value "dac_bridge_1") (footprint "") + ) + (path "/add3225f-3e6d-4227-96ab-280bbfdb0b0e" + (reference "U50") (unit 1) (value "dac_bridge_1") (footprint "") + ) + (path "/2d6d2596-0bd1-408d-b636-28bd7ea25117" + (reference "U51") (unit 1) (value "dac_bridge_1") (footprint "") + ) + (path "/7d873795-20de-48d6-abfa-aea26ff695ee" + (reference "U52") (unit 1) (value "plot_v1") (footprint "") + ) + (path "/77328b82-1e28-4df8-852a-994a61b257b8" + (reference "U53") (unit 1) (value "plot_v1") (footprint "") + ) + (path "/48c30ccc-2a6d-4e8e-bc04-7eaeebfe1d39" + (reference "U54") (unit 1) (value "plot_v1") (footprint "") + ) + (path "/7827159b-7c15-4d47-bca9-52d070e665f3" + (reference "U55") (unit 1) (value "plot_v1") (footprint "") + ) + (path "/d0f9b2af-e954-43c7-bac4-caace966e910" + (reference "U56") (unit 1) (value "plot_v1") (footprint "") + ) + (path "/4c99e314-7a3c-4174-b3f3-10beb413f951" + (reference "U57") (unit 1) (value "plot_v1") (footprint "") + ) + (path "/73c86e42-b821-441a-aa8d-89e2dd76267f" + (reference "U58") (unit 1) (value "plot_v1") (footprint "") + ) + (path "/980fac4b-0606-4812-9603-9d722fa4bedf" + (reference "U59") (unit 1) (value "plot_v1") (footprint "") + ) + ) +) diff --git a/library/SubcircuitLibrary/CD4026B/CD4026B.sub b/library/SubcircuitLibrary/CD4026B/CD4026B.sub new file mode 100644 index 000000000..ec6bcaaac --- /dev/null +++ b/library/SubcircuitLibrary/CD4026B/CD4026B.sub @@ -0,0 +1,208 @@ +* Subcircuit CD4026B +.subckt CD4026B clk_dig clk_inhibit_dig displayenablein_dig displayenablein_dig net-_u2-pad5_ net-_u2-pad6_ net-_u2-pad7_ unconnected-_u2-pad8_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u18-pad3_ reset_dig unconnected-_u2-pad16_ +.title kicad schematic +* u7 net-_u13-pad2_ net-_u15-pad2_ net-_u11-pad2_ d_and +* u9 net-_u15-pad1_ net-_u10-pad5_ net-_u11-pad1_ d_and +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_or +* u20 net-_u17-pad1_ net-_u12-pad5_ net-_u20-pad3_ d_or +* u21 net-_u10-pad1_ net-_u10-pad6_ net-_u21-pad3_ d_or +* u12 net-_u10-pad5_ net-_u10-pad2_ net-_u1-pad2_ reset_dig net-_u12-pad5_ net-_u12-pad6_ d_dff +* u8 net-_u15-pad1_ net-_u10-pad2_ net-_u1-pad2_ reset_dig net-_u10-pad1_ net-_u13-pad2_ d_dff +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad2_ reset_dig net-_u10-pad5_ net-_u10-pad6_ d_dff +* u1 gnd net-_u1-pad2_ adc_bridge_1 +* u3 clk_inhibit_dig net-_u3-pad2_ d_inverter +* u5 net-_u12-pad6_ net-_u10-pad2_ net-_u1-pad2_ reset_dig net-_u17-pad1_ net-_u15-pad2_ d_dff +* u6 net-_u17-pad1_ net-_u10-pad2_ net-_u1-pad2_ reset_dig net-_u15-pad1_ net-_u17-pad2_ d_dff +* u4 clk_dig net-_u3-pad2_ net-_u10-pad2_ d_and +* u22 net-_u13-pad2_ net-_u10-pad5_ unconnected-_u22-pad3_ d_or +* u13 net-_u12-pad5_ net-_u13-pad2_ net-_u13-pad3_ d_and +* u14 net-_u10-pad6_ net-_u12-pad5_ net-_u14-pad3_ d_or +* u19 net-_u15-pad1_ net-_u13-pad2_ net-_u19-pad3_ d_or +* u16 net-_u15-pad2_ net-_u12-pad6_ net-_u16-pad3_ d_or +* u18 net-_u17-pad2_ net-_u10-pad1_ net-_u18-pad3_ d_or +* u17 net-_u17-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_or +* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_or +* u37 net-_u30-pad3_ net-_u18-pad3_ net-_u37-pad3_ d_and +* u29 net-_u19-pad3_ net-_u14-pad3_ net-_u29-pad3_ d_and +* u36 net-_u29-pad3_ net-_u15-pad3_ net-_u36-pad3_ d_and +* u30 net-_u20-pad3_ net-_u17-pad3_ net-_u30-pad3_ d_and +* u33 net-_u18-pad3_ displayenablein_dig net-_u2-pad13_ d_and +* u32 net-_u24-pad3_ displayenablein_dig net-_u2-pad12_ d_and +* u38 net-_u36-pad3_ displayenablein_dig net-_u2-pad9_ d_and +* u24 net-_u16-pad3_ net-_u17-pad3_ net-_u24-pad3_ d_and +* u26 net-_u14-pad3_ net-_u15-pad3_ net-_u26-pad3_ d_and +* u25 net-_u2-pad5_ cout dac_bridge_1 +* u31 net-_u26-pad3_ displayenablein_dig net-_u2-pad10_ d_and +* u23 net-_u12-pad5_ net-_u2-pad5_ d_inverter +* u27 cout plot_v1 +* u56 d plot_v1 +* u52 ungated_c plot_v1 +* u53 a plot_v1 +* u55 b plot_v1 +* u54 c plot_v1 +* u59 e plot_v1 +* u35 net-_u13-pad3_ net-_u15-pad1_ net-_u35-pad3_ d_or +* u28 displayenablein_dig displayenableout dac_bridge_1 +* u34 displayenableout plot_v1 +* u40 net-_u35-pad3_ displayenablein_dig net-_u2-pad7_ d_and +* u39 net-_u37-pad3_ net-_u21-pad3_ net-_u39-pad3_ d_and +* u41 net-_u39-pad3_ displayenablein_dig net-_u41-pad3_ d_and +* u42 net-_u11-pad3_ displayenablein_dig net-_u2-pad6_ d_and +* u47 net-_u2-pad12_ b dac_bridge_1 +* u46 net-_u2-pad10_ a dac_bridge_1 +* u45 net-_u2-pad9_ d dac_bridge_1 +* u48 net-_u2-pad13_ c dac_bridge_1 +* u44 net-_u18-pad3_ ungated_c dac_bridge_1 +* u50 net-_u2-pad7_ g dac_bridge_1 +* u49 net-_u2-pad6_ f dac_bridge_1 +* u43 net-_u41-pad3_ net-_u2-pad11_ d_inverter +* u51 net-_u2-pad11_ e dac_bridge_1 +* u58 g plot_v1 +* u57 f plot_v1 +a1 [net-_u13-pad2_ net-_u15-pad2_ ] net-_u11-pad2_ u7 +a2 [net-_u15-pad1_ net-_u10-pad5_ ] net-_u11-pad1_ u9 +a3 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a4 [net-_u17-pad1_ net-_u12-pad5_ ] net-_u20-pad3_ u20 +a5 [net-_u10-pad1_ net-_u10-pad6_ ] net-_u21-pad3_ u21 +a6 net-_u10-pad5_ net-_u10-pad2_ net-_u1-pad2_ reset_dig net-_u12-pad5_ net-_u12-pad6_ u12 +a7 net-_u15-pad1_ net-_u10-pad2_ net-_u1-pad2_ reset_dig net-_u10-pad1_ net-_u13-pad2_ u8 +a8 net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad2_ reset_dig net-_u10-pad5_ net-_u10-pad6_ u10 +a9 [gnd ] [net-_u1-pad2_ ] u1 +a10 clk_inhibit_dig net-_u3-pad2_ u3 +a11 net-_u12-pad6_ net-_u10-pad2_ net-_u1-pad2_ reset_dig net-_u17-pad1_ net-_u15-pad2_ u5 +a12 net-_u17-pad1_ net-_u10-pad2_ net-_u1-pad2_ reset_dig net-_u15-pad1_ net-_u17-pad2_ u6 +a13 [clk_dig net-_u3-pad2_ ] net-_u10-pad2_ u4 +a14 [net-_u13-pad2_ net-_u10-pad5_ ] unconnected-_u22-pad3_ u22 +a15 [net-_u12-pad5_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a16 [net-_u10-pad6_ net-_u12-pad5_ ] net-_u14-pad3_ u14 +a17 [net-_u15-pad1_ net-_u13-pad2_ ] net-_u19-pad3_ u19 +a18 [net-_u15-pad2_ net-_u12-pad6_ ] net-_u16-pad3_ u16 +a19 [net-_u17-pad2_ net-_u10-pad1_ ] net-_u18-pad3_ u18 +a20 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17 +a21 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a22 [net-_u30-pad3_ net-_u18-pad3_ ] net-_u37-pad3_ u37 +a23 [net-_u19-pad3_ net-_u14-pad3_ ] net-_u29-pad3_ u29 +a24 [net-_u29-pad3_ net-_u15-pad3_ ] net-_u36-pad3_ u36 +a25 [net-_u20-pad3_ net-_u17-pad3_ ] net-_u30-pad3_ u30 +a26 [net-_u18-pad3_ displayenablein_dig ] net-_u2-pad13_ u33 +a27 [net-_u24-pad3_ displayenablein_dig ] net-_u2-pad12_ u32 +a28 [net-_u36-pad3_ displayenablein_dig ] net-_u2-pad9_ u38 +a29 [net-_u16-pad3_ net-_u17-pad3_ ] net-_u24-pad3_ u24 +a30 [net-_u14-pad3_ net-_u15-pad3_ ] net-_u26-pad3_ u26 +a31 [net-_u2-pad5_ ] [cout ] u25 +a32 [net-_u26-pad3_ displayenablein_dig ] net-_u2-pad10_ u31 +a33 net-_u12-pad5_ net-_u2-pad5_ u23 +a34 [net-_u13-pad3_ net-_u15-pad1_ ] net-_u35-pad3_ u35 +a35 [displayenablein_dig ] [displayenableout ] u28 +a36 [net-_u35-pad3_ displayenablein_dig ] net-_u2-pad7_ u40 +a37 [net-_u37-pad3_ net-_u21-pad3_ ] net-_u39-pad3_ u39 +a38 [net-_u39-pad3_ displayenablein_dig ] net-_u41-pad3_ u41 +a39 [net-_u11-pad3_ displayenablein_dig ] net-_u2-pad6_ u42 +a40 [net-_u2-pad12_ ] [b ] u47 +a41 [net-_u2-pad10_ ] [a ] u46 +a42 [net-_u2-pad9_ ] [d ] u45 +a43 [net-_u2-pad13_ ] [c ] u48 +a44 [net-_u18-pad3_ ] [ungated_c ] u44 +a45 [net-_u2-pad7_ ] [g ] u50 +a46 [net-_u2-pad6_ ] [f ] u49 +a47 net-_u41-pad3_ net-_u2-pad11_ u43 +a48 [net-_u2-pad11_ ] [e ] u51 +* Schematic Name: d_and, Ngspice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u11 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u20 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u21 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u12 d_dff(clk_delay=1.0e-12 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-12 fall_delay=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u8 d_dff(clk_delay=1.0e-12 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-12 fall_delay=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u10 d_dff(clk_delay=1.0e-12 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-12 fall_delay=1.0e-12 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u1 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u5 d_dff(clk_delay=1.0e-12 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-12 fall_delay=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u6 d_dff(clk_delay=1.0e-12 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-12 fall_delay=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u22 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u14 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u19 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u16 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u18 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u15 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u37 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u25 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u35 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u28 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u40 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u39 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u41 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u42 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u47 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u46 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u45 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u48 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u44 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u50 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u49 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u51 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Control Statements + +.ends CD4026B \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4026B/CD4026B_Previous_Values.xml b/library/SubcircuitLibrary/CD4026B/CD4026B_Previous_Values.xml new file mode 100644 index 000000000..97b77d55b --- /dev/null +++ b/library/SubcircuitLibrary/CD4026B/CD4026B_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andd_ord_ord_ord_dff1.0e-121.0e-121.0e-12d_dff1.0e-121.0e-121.0e-12d_dff1.0e-121.0e-121.0e-12adc_bridged_inverterd_dff1.0e-121.0e-121.0e-12d_dff1.0e-121.0e-121.0e-12d_andd_ord_andd_ord_ord_ord_ord_ord_ord_andd_andd_andd_andd_andd_andd_andd_andd_anddac_bridged_andd_inverterd_ordac_bridged_andd_andd_andd_anddac_bridgedac_bridgedac_bridgedac_bridgedac_bridgedac_bridgedac_bridged_inverterdac_bridgetruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4026B/analysis b/library/SubcircuitLibrary/CD4026B/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/CD4026B/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4029B/CD4029B.cir b/library/SubcircuitLibrary/CD4029B/CD4029B.cir new file mode 100644 index 000000000..d92e2dc45 --- /dev/null +++ b/library/SubcircuitLibrary/CD4029B/CD4029B.cir @@ -0,0 +1,49 @@ +.title KiCad schematic +U18 J2 PE Net-_U18-Pad3_ d_and +U20 Q1 Net-_U20-Pad2_ Net-_U20-Pad3_ d_and +U9 J1 PE Net-_U11-Pad3_ d_and +U2 PE Q4 J4 J1 cin_bar Q1 CO unconnected-_U2-Pad8_ B/D up/d Q2 J2 J3 Q3 clk unconnected-_U2-Pad16_ PORT +U6 J1 Net-_U10-Pad2_ d_inverter +U4 Net-_U4-Pad1_ interm dac_bridge_1 +U1 cin_bar Net-_U1-Pad2_ d_inverter +U3 clk Net-_U1-Pad2_ Net-_U11-Pad2_ d_and +U5 GND Net-_U5-Pad2_ adc_bridge_1 +U7 Net-_U5-Pad2_ Net-_U11-Pad1_ d_inverter +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ Net-_U11-Pad4_ Q1 Net-_U11-Pad6_ d_tff +U19 PE Net-_U16-Pad2_ Net-_U19-Pad3_ d_and +U10 PE Net-_U10-Pad2_ Net-_U10-Pad3_ d_and +U14 Net-_U11-Pad6_ Net-_U13-Pad2_ Net-_U14-Pad3_ d_and +U13 up/d Net-_U13-Pad2_ d_inverter +U15 up/d Q1 Net-_U15-Pad3_ d_and +U17 Net-_U15-Pad3_ Net-_U14-Pad3_ Net-_U17-Pad3_ d_or +U8 Net-_U20-Pad3_ B/D Net-_U12-Pad2_ d_and +U12 Net-_U10-Pad3_ Net-_U12-Pad2_ Net-_U11-Pad4_ d_or +U16 J2 Net-_U16-Pad2_ d_inverter +U37 Q3 Net-_U36-Pad1_ d_inverter +U41 J4 PE Net-_U41-Pad3_ d_and +U34 Net-_U23-Pad3_ Q3 Net-_U34-Pad3_ d_and +U35 Net-_U33-Pad6_ Net-_U24-Pad3_ Net-_U35-Pad3_ d_and +U40 Net-_U34-Pad3_ Net-_U35-Pad3_ Net-_U40-Pad3_ d_or +U38 Net-_U25-Pad3_ Q3 Net-_U38-Pad3_ d_and +U36 Net-_U36-Pad1_ Q4 Net-_U32-Pad2_ d_and +U44 Net-_U38-Pad3_ Q4 Net-_U44-Pad3_ d_and +U42 PE Net-_U39-Pad2_ Net-_U42-Pad3_ d_and +U39 J4 Net-_U39-Pad2_ d_inverter +U43 Net-_U42-Pad3_ Net-_U12-Pad2_ Net-_U4-Pad1_ d_or +U30 J3 PE Net-_U30-Pad3_ d_and +U23 Net-_U15-Pad3_ Q2 Net-_U23-Pad3_ d_and +U27 Net-_U23-Pad3_ Net-_U24-Pad3_ Net-_U27-Pad3_ d_or +U25 Q1 Q2 Net-_U25-Pad3_ d_and +U28 Q2 Net-_U28-Pad2_ d_inverter +U32 Net-_U28-Pad2_ Net-_U32-Pad2_ Net-_U20-Pad2_ d_and +U24 Net-_U21-Pad6_ Net-_U14-Pad3_ Net-_U24-Pad3_ d_and +U21 Net-_U17-Pad3_ Net-_U11-Pad2_ Net-_U18-Pad3_ Net-_U21-Pad4_ Q2 Net-_U21-Pad6_ d_tff +U33 Net-_U27-Pad3_ Net-_U11-Pad2_ Net-_U30-Pad3_ Net-_U29-Pad3_ Q3 Net-_U33-Pad6_ d_tff +U31 PE Net-_U26-Pad2_ Net-_U29-Pad1_ d_and +U29 Net-_U29-Pad1_ Net-_U12-Pad2_ Net-_U29-Pad3_ d_or +U22 Net-_U19-Pad3_ Net-_U12-Pad2_ Net-_U21-Pad4_ d_or +U26 J3 Net-_U26-Pad2_ d_inverter +U45 Net-_U40-Pad3_ Net-_U11-Pad2_ Net-_U41-Pad3_ Net-_U4-Pad1_ Q4 unconnected-_U45-Pad6_ d_tff +U46 Net-_U44-Pad3_ Net-_U46-Pad2_ d_inverter +U47 Net-_U46-Pad2_ clk CO d_or +.end diff --git a/library/SubcircuitLibrary/CD4029B/CD4029B.cir.out b/library/SubcircuitLibrary/CD4029B/CD4029B.cir.out new file mode 100644 index 000000000..ac54c1ff4 --- /dev/null +++ b/library/SubcircuitLibrary/CD4029B/CD4029B.cir.out @@ -0,0 +1,196 @@ +.title kicad schematic + +* u18 j2 pe net-_u18-pad3_ d_and +* u20 q1 net-_u20-pad2_ net-_u20-pad3_ d_and +* u9 j1 pe net-_u11-pad3_ d_and +* u2 pe q4 j4 j1 cin_bar q1 co unconnected-_u2-pad8_ b/d up/d q2 j2 j3 q3 clk unconnected-_u2-pad16_ port +* u6 j1 net-_u10-pad2_ d_inverter +* u4 net-_u4-pad1_ interm dac_bridge_1 +* u1 cin_bar net-_u1-pad2_ d_inverter +* u3 clk net-_u1-pad2_ net-_u11-pad2_ d_and +* u5 gnd net-_u5-pad2_ adc_bridge_1 +* u7 net-_u5-pad2_ net-_u11-pad1_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ net-_u11-pad4_ q1 net-_u11-pad6_ d_tff +* u19 pe net-_u16-pad2_ net-_u19-pad3_ d_and +* u10 pe net-_u10-pad2_ net-_u10-pad3_ d_and +* u14 net-_u11-pad6_ net-_u13-pad2_ net-_u14-pad3_ d_and +* u13 up/d net-_u13-pad2_ d_inverter +* u15 up/d q1 net-_u15-pad3_ d_and +* u17 net-_u15-pad3_ net-_u14-pad3_ net-_u17-pad3_ d_or +* u8 net-_u20-pad3_ b/d net-_u12-pad2_ d_and +* u12 net-_u10-pad3_ net-_u12-pad2_ net-_u11-pad4_ d_or +* u16 j2 net-_u16-pad2_ d_inverter +* u37 q3 net-_u36-pad1_ d_inverter +* u41 j4 pe net-_u41-pad3_ d_and +* u34 net-_u23-pad3_ q3 net-_u34-pad3_ d_and +* u35 net-_u33-pad6_ net-_u24-pad3_ net-_u35-pad3_ d_and +* u40 net-_u34-pad3_ net-_u35-pad3_ net-_u40-pad3_ d_or +* u38 net-_u25-pad3_ q3 net-_u38-pad3_ d_and +* u36 net-_u36-pad1_ q4 net-_u32-pad2_ d_and +* u44 net-_u38-pad3_ q4 net-_u44-pad3_ d_and +* u42 pe net-_u39-pad2_ net-_u42-pad3_ d_and +* u39 j4 net-_u39-pad2_ d_inverter +* u43 net-_u42-pad3_ net-_u12-pad2_ net-_u4-pad1_ d_or +* u30 j3 pe net-_u30-pad3_ d_and +* u23 net-_u15-pad3_ q2 net-_u23-pad3_ d_and +* u27 net-_u23-pad3_ net-_u24-pad3_ net-_u27-pad3_ d_or +* u25 q1 q2 net-_u25-pad3_ d_and +* u28 q2 net-_u28-pad2_ d_inverter +* u32 net-_u28-pad2_ net-_u32-pad2_ net-_u20-pad2_ d_and +* u24 net-_u21-pad6_ net-_u14-pad3_ net-_u24-pad3_ d_and +* u21 net-_u17-pad3_ net-_u11-pad2_ net-_u18-pad3_ net-_u21-pad4_ q2 net-_u21-pad6_ d_tff +* u33 net-_u27-pad3_ net-_u11-pad2_ net-_u30-pad3_ net-_u29-pad3_ q3 net-_u33-pad6_ d_tff +* u31 pe net-_u26-pad2_ net-_u29-pad1_ d_and +* u29 net-_u29-pad1_ net-_u12-pad2_ net-_u29-pad3_ d_or +* u22 net-_u19-pad3_ net-_u12-pad2_ net-_u21-pad4_ d_or +* u26 j3 net-_u26-pad2_ d_inverter +* u45 net-_u40-pad3_ net-_u11-pad2_ net-_u41-pad3_ net-_u4-pad1_ q4 unconnected-_u45-pad6_ d_tff +* u46 net-_u44-pad3_ net-_u46-pad2_ d_inverter +* u47 net-_u46-pad2_ clk co d_or +a1 [j2 pe ] net-_u18-pad3_ u18 +a2 [q1 net-_u20-pad2_ ] net-_u20-pad3_ u20 +a3 [j1 pe ] net-_u11-pad3_ u9 +a4 j1 net-_u10-pad2_ u6 +a5 [net-_u4-pad1_ ] [interm ] u4 +a6 cin_bar net-_u1-pad2_ u1 +a7 [clk net-_u1-pad2_ ] net-_u11-pad2_ u3 +a8 [gnd ] [net-_u5-pad2_ ] u5 +a9 net-_u5-pad2_ net-_u11-pad1_ u7 +a10 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ net-_u11-pad4_ q1 net-_u11-pad6_ u11 +a11 [pe net-_u16-pad2_ ] net-_u19-pad3_ u19 +a12 [pe net-_u10-pad2_ ] net-_u10-pad3_ u10 +a13 [net-_u11-pad6_ net-_u13-pad2_ ] net-_u14-pad3_ u14 +a14 up/d net-_u13-pad2_ u13 +a15 [up/d q1 ] net-_u15-pad3_ u15 +a16 [net-_u15-pad3_ net-_u14-pad3_ ] net-_u17-pad3_ u17 +a17 [net-_u20-pad3_ b/d ] net-_u12-pad2_ u8 +a18 [net-_u10-pad3_ net-_u12-pad2_ ] net-_u11-pad4_ u12 +a19 j2 net-_u16-pad2_ u16 +a20 q3 net-_u36-pad1_ u37 +a21 [j4 pe ] net-_u41-pad3_ u41 +a22 [net-_u23-pad3_ q3 ] net-_u34-pad3_ u34 +a23 [net-_u33-pad6_ net-_u24-pad3_ ] net-_u35-pad3_ u35 +a24 [net-_u34-pad3_ net-_u35-pad3_ ] net-_u40-pad3_ u40 +a25 [net-_u25-pad3_ q3 ] net-_u38-pad3_ u38 +a26 [net-_u36-pad1_ q4 ] net-_u32-pad2_ u36 +a27 [net-_u38-pad3_ q4 ] net-_u44-pad3_ u44 +a28 [pe net-_u39-pad2_ ] net-_u42-pad3_ u42 +a29 j4 net-_u39-pad2_ u39 +a30 [net-_u42-pad3_ net-_u12-pad2_ ] net-_u4-pad1_ u43 +a31 [j3 pe ] net-_u30-pad3_ u30 +a32 [net-_u15-pad3_ q2 ] net-_u23-pad3_ u23 +a33 [net-_u23-pad3_ net-_u24-pad3_ ] net-_u27-pad3_ u27 +a34 [q1 q2 ] net-_u25-pad3_ u25 +a35 q2 net-_u28-pad2_ u28 +a36 [net-_u28-pad2_ net-_u32-pad2_ ] net-_u20-pad2_ u32 +a37 [net-_u21-pad6_ net-_u14-pad3_ ] net-_u24-pad3_ u24 +a38 net-_u17-pad3_ net-_u11-pad2_ net-_u18-pad3_ net-_u21-pad4_ q2 net-_u21-pad6_ u21 +a39 net-_u27-pad3_ net-_u11-pad2_ net-_u30-pad3_ net-_u29-pad3_ q3 net-_u33-pad6_ u33 +a40 [pe net-_u26-pad2_ ] net-_u29-pad1_ u31 +a41 [net-_u29-pad1_ net-_u12-pad2_ ] net-_u29-pad3_ u29 +a42 [net-_u19-pad3_ net-_u12-pad2_ ] net-_u21-pad4_ u22 +a43 j3 net-_u26-pad2_ u26 +a44 net-_u40-pad3_ net-_u11-pad2_ net-_u41-pad3_ net-_u4-pad1_ q4 unconnected-_u45-pad6_ u45 +a45 net-_u44-pad3_ net-_u46-pad2_ u46 +a46 [net-_u46-pad2_ clk ] co u47 +* Schematic Name: d_and, Ngspice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u4 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u5 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tff, Ngspice Name: d_tff +.model u11 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u12 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u41 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u35 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u40 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u44 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u42 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u39 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u43 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u27 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tff, Ngspice Name: d_tff +.model u21 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tff, Ngspice Name: d_tff +.model u33 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u29 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u22 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tff, Ngspice Name: d_tff +.model u45 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u46 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u47 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4029B/CD4029B.kicad_sch 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"/2de04b91-0824-4bb2-ab58-9f46cc37edc3" + (reference "U40") (unit 1) (value "d_or") (footprint "") + ) + (path "/0bc90df7-c6d9-429e-9ce1-619b3f2ee485" + (reference "U41") (unit 1) (value "d_and") (footprint "") + ) + (path "/68f8f006-0954-4ab0-a928-63f0254efb7a" + (reference "U42") (unit 1) (value "d_and") (footprint "") + ) + (path "/d8660bf0-1600-4c20-a47e-3b570790d9fd" + (reference "U43") (unit 1) (value "d_or") (footprint "") + ) + (path "/6f2642c8-2bb0-4e42-b4d7-039596e6fc5f" + (reference "U44") (unit 1) (value "d_and") (footprint "") + ) + (path "/75944545-d06f-484f-949e-1a127dcdebb1" + (reference "U45") (unit 1) (value "d_tff") (footprint "") + ) + (path "/3a044cf3-0812-4f05-adbe-cce1a691278f" + (reference "U46") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/8a15313a-ed51-4765-a570-93edac06fa13" + (reference "U47") (unit 1) (value "d_or") (footprint "") + ) + ) +) diff --git a/library/SubcircuitLibrary/CD4029B/CD4029B.sub b/library/SubcircuitLibrary/CD4029B/CD4029B.sub new file mode 100644 index 000000000..75d2a8847 --- /dev/null +++ b/library/SubcircuitLibrary/CD4029B/CD4029B.sub @@ -0,0 +1,190 @@ +* Subcircuit CD4029B +.subckt CD4029B pe q4 j4 j1 cin_bar q1 co unconnected-_u2-pad8_ b/d up/d q2 j2 j3 q3 clk unconnected-_u2-pad16_ +.title kicad schematic +* u18 j2 pe net-_u18-pad3_ d_and +* u20 q1 net-_u20-pad2_ net-_u20-pad3_ d_and +* u9 j1 pe net-_u11-pad3_ d_and +* u6 j1 net-_u10-pad2_ d_inverter +* u4 net-_u4-pad1_ interm dac_bridge_1 +* u1 cin_bar net-_u1-pad2_ d_inverter +* u3 clk net-_u1-pad2_ net-_u11-pad2_ d_and +* u5 gnd net-_u5-pad2_ adc_bridge_1 +* u7 net-_u5-pad2_ net-_u11-pad1_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ net-_u11-pad4_ q1 net-_u11-pad6_ d_tff +* u19 pe net-_u16-pad2_ net-_u19-pad3_ d_and +* u10 pe net-_u10-pad2_ net-_u10-pad3_ d_and +* u14 net-_u11-pad6_ net-_u13-pad2_ net-_u14-pad3_ d_and +* u13 up/d net-_u13-pad2_ d_inverter +* u15 up/d q1 net-_u15-pad3_ d_and +* u17 net-_u15-pad3_ net-_u14-pad3_ net-_u17-pad3_ d_or +* u8 net-_u20-pad3_ b/d net-_u12-pad2_ d_and +* u12 net-_u10-pad3_ net-_u12-pad2_ net-_u11-pad4_ d_or +* u16 j2 net-_u16-pad2_ d_inverter +* u37 q3 net-_u36-pad1_ d_inverter +* u41 j4 pe net-_u41-pad3_ d_and +* u34 net-_u23-pad3_ q3 net-_u34-pad3_ d_and +* u35 net-_u33-pad6_ net-_u24-pad3_ net-_u35-pad3_ d_and +* u40 net-_u34-pad3_ net-_u35-pad3_ net-_u40-pad3_ d_or +* u38 net-_u25-pad3_ q3 net-_u38-pad3_ d_and +* u36 net-_u36-pad1_ q4 net-_u32-pad2_ d_and +* u44 net-_u38-pad3_ q4 net-_u44-pad3_ d_and +* u42 pe net-_u39-pad2_ net-_u42-pad3_ d_and +* u39 j4 net-_u39-pad2_ d_inverter +* u43 net-_u42-pad3_ net-_u12-pad2_ net-_u4-pad1_ d_or +* u30 j3 pe net-_u30-pad3_ d_and +* u23 net-_u15-pad3_ q2 net-_u23-pad3_ d_and +* u27 net-_u23-pad3_ net-_u24-pad3_ net-_u27-pad3_ d_or +* u25 q1 q2 net-_u25-pad3_ d_and +* u28 q2 net-_u28-pad2_ d_inverter +* u32 net-_u28-pad2_ net-_u32-pad2_ net-_u20-pad2_ d_and +* u24 net-_u21-pad6_ net-_u14-pad3_ net-_u24-pad3_ d_and +* u21 net-_u17-pad3_ net-_u11-pad2_ net-_u18-pad3_ net-_u21-pad4_ q2 net-_u21-pad6_ d_tff +* u33 net-_u27-pad3_ net-_u11-pad2_ net-_u30-pad3_ net-_u29-pad3_ q3 net-_u33-pad6_ d_tff +* u31 pe net-_u26-pad2_ net-_u29-pad1_ d_and +* u29 net-_u29-pad1_ net-_u12-pad2_ net-_u29-pad3_ d_or +* u22 net-_u19-pad3_ net-_u12-pad2_ net-_u21-pad4_ d_or +* u26 j3 net-_u26-pad2_ d_inverter +* u45 net-_u40-pad3_ net-_u11-pad2_ net-_u41-pad3_ net-_u4-pad1_ q4 unconnected-_u45-pad6_ d_tff +* u46 net-_u44-pad3_ net-_u46-pad2_ d_inverter +* u47 net-_u46-pad2_ clk co d_or +a1 [j2 pe ] net-_u18-pad3_ u18 +a2 [q1 net-_u20-pad2_ ] net-_u20-pad3_ u20 +a3 [j1 pe ] net-_u11-pad3_ u9 +a4 j1 net-_u10-pad2_ u6 +a5 [net-_u4-pad1_ ] [interm ] u4 +a6 cin_bar net-_u1-pad2_ u1 +a7 [clk net-_u1-pad2_ ] net-_u11-pad2_ u3 +a8 [gnd ] [net-_u5-pad2_ ] u5 +a9 net-_u5-pad2_ net-_u11-pad1_ u7 +a10 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ net-_u11-pad4_ q1 net-_u11-pad6_ u11 +a11 [pe net-_u16-pad2_ ] net-_u19-pad3_ u19 +a12 [pe net-_u10-pad2_ ] net-_u10-pad3_ u10 +a13 [net-_u11-pad6_ net-_u13-pad2_ ] net-_u14-pad3_ u14 +a14 up/d net-_u13-pad2_ u13 +a15 [up/d q1 ] net-_u15-pad3_ u15 +a16 [net-_u15-pad3_ net-_u14-pad3_ ] net-_u17-pad3_ u17 +a17 [net-_u20-pad3_ b/d ] net-_u12-pad2_ u8 +a18 [net-_u10-pad3_ net-_u12-pad2_ ] net-_u11-pad4_ u12 +a19 j2 net-_u16-pad2_ u16 +a20 q3 net-_u36-pad1_ u37 +a21 [j4 pe ] net-_u41-pad3_ u41 +a22 [net-_u23-pad3_ q3 ] net-_u34-pad3_ u34 +a23 [net-_u33-pad6_ net-_u24-pad3_ ] net-_u35-pad3_ u35 +a24 [net-_u34-pad3_ net-_u35-pad3_ ] net-_u40-pad3_ u40 +a25 [net-_u25-pad3_ q3 ] net-_u38-pad3_ u38 +a26 [net-_u36-pad1_ q4 ] net-_u32-pad2_ u36 +a27 [net-_u38-pad3_ q4 ] net-_u44-pad3_ u44 +a28 [pe net-_u39-pad2_ ] net-_u42-pad3_ u42 +a29 j4 net-_u39-pad2_ u39 +a30 [net-_u42-pad3_ net-_u12-pad2_ ] net-_u4-pad1_ u43 +a31 [j3 pe ] net-_u30-pad3_ u30 +a32 [net-_u15-pad3_ q2 ] net-_u23-pad3_ u23 +a33 [net-_u23-pad3_ net-_u24-pad3_ ] net-_u27-pad3_ u27 +a34 [q1 q2 ] net-_u25-pad3_ u25 +a35 q2 net-_u28-pad2_ u28 +a36 [net-_u28-pad2_ net-_u32-pad2_ ] net-_u20-pad2_ u32 +a37 [net-_u21-pad6_ net-_u14-pad3_ ] net-_u24-pad3_ u24 +a38 net-_u17-pad3_ net-_u11-pad2_ net-_u18-pad3_ net-_u21-pad4_ q2 net-_u21-pad6_ u21 +a39 net-_u27-pad3_ net-_u11-pad2_ net-_u30-pad3_ net-_u29-pad3_ q3 net-_u33-pad6_ u33 +a40 [pe net-_u26-pad2_ ] net-_u29-pad1_ u31 +a41 [net-_u29-pad1_ net-_u12-pad2_ ] net-_u29-pad3_ u29 +a42 [net-_u19-pad3_ net-_u12-pad2_ ] net-_u21-pad4_ u22 +a43 j3 net-_u26-pad2_ u26 +a44 net-_u40-pad3_ net-_u11-pad2_ net-_u41-pad3_ net-_u4-pad1_ q4 unconnected-_u45-pad6_ u45 +a45 net-_u44-pad3_ net-_u46-pad2_ u46 +a46 [net-_u46-pad2_ clk ] co u47 +* Schematic Name: d_and, Ngspice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u4 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u5 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tff, Ngspice Name: d_tff +.model u11 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u12 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u41 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u35 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u40 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u44 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u42 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u39 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u43 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u27 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tff, Ngspice Name: d_tff +.model u21 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tff, Ngspice Name: d_tff +.model u33 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u29 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u22 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tff, Ngspice Name: d_tff +.model u45 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u46 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u47 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends CD4029B \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4029B/CD4029B_Previous_Values.xml b/library/SubcircuitLibrary/CD4029B/CD4029B_Previous_Values.xml new file mode 100644 index 000000000..1b6fcde44 --- /dev/null +++ b/library/SubcircuitLibrary/CD4029B/CD4029B_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andd_andd_inverterdac_bridged_inverterd_andadc_bridged_inverterd_tff1.0e-9d_andd_andd_andd_inverterd_andd_ord_andd_ord_inverterd_inverterd_andd_andd_andd_ord_andd_andd_andd_andd_inverterd_ord_andd_andd_ord_andd_inverterd_andd_andd_tff1.0e-9d_tff1.0e-9d_andd_ord_ord_inverterd_tff1.0e-9d_inverterd_ortruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4029B/analysis b/library/SubcircuitLibrary/CD4029B/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/CD4029B/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4089B/CD4089B.cir b/library/SubcircuitLibrary/CD4089B/CD4089B.cir new file mode 100644 index 000000000..b6b289b50 --- /dev/null +++ b/library/SubcircuitLibrary/CD4089B/CD4089B.cir @@ -0,0 +1,42 @@ +.title KiCad schematic +U7 Net-_U16-Pad1_ Qa_bar set_dig reset_dig Qb Qb_bar d_tff +U6 Net-_U16-Pad1_ clk_dig set_dig reset_dig Qa Qa_bar d_tff +U2 GND Net-_U2-Pad2_ adc_bridge_1 +U5 Net-_U2-Pad2_ Net-_U16-Pad1_ d_inverter +U16 Net-_U16-Pad1_ Qc_bar set_dig reset_dig Qd Qd_bar d_tff +U8 Net-_U16-Pad1_ Qb_bar set_dig reset_dig Qc Qc_bar d_tff +U12 Cdig Qb_bar Net-_U12-Pad3_ d_and +U14 Net-_U14-Pad1_ Qc Net-_U14-Pad3_ d_and +U21 Qb Net-_U15-Pad3_ I_dig d_and +U10 Qd Qa Net-_U10-Pad3_ d_and +U13 Ddig Qa_bar Net-_U13-Pad3_ d_and +U18 Net-_U12-Pad3_ Qa Net-_U18-Pad3_ d_and +U9 Bdig Qa Net-_U14-Pad1_ d_and +U1 I_dig Cdig Ddig set_dig out_bar_dig out_dig inhibit_out_dig unconnected-_U1-Pad8_ clk_dig strobe_dig inhibit_in_dig cascade_dig reset_dig Adig Bdig unconnected-_U1-Pad16_ PORT +U38 Net-_U34-Pad2_ Net-_U35-Pad3_ Net-_U38-Pad3_ d_and +U34 strobe_dig Net-_U34-Pad2_ d_inverter +U33 cascade_dig Net-_U33-Pad2_ out_dig d_or +U41 Net-_U38-Pad3_ Net-_U39-Pad2_ Net-_U33-Pad2_ d_and +U39 inhibit_in_dig Net-_U39-Pad2_ d_inverter +U35 Net-_U28-Pad2_ Net-_U27-Pad3_ Net-_U35-Pad3_ d_and +U30 out_dig out dac_bridge_1 +U32 I_dig 15_out dac_bridge_1 +U31 out_bar_dig out_bar dac_bridge_1 +U43 inhibit_out_dig inhibit_out dac_bridge_1 +U17 Net-_U11-Pad3_ Qc Net-_U17-Pad3_ d_and +U20 Qb Net-_U14-Pad3_ Net-_U20-Pad3_ d_and +U25 Net-_U20-Pad3_ Net-_U23-Pad3_ Net-_U25-Pad3_ d_or +U24 Net-_U22-Pad3_ Qa Net-_U24-Pad3_ d_and +U28 clk_dig Net-_U28-Pad2_ d_inverter +U27 Net-_U24-Pad3_ Net-_U25-Pad3_ Net-_U27-Pad3_ d_or +U26 Qb_bar Qc_bar Net-_U26-Pad3_ d_and +U23 Net-_U18-Pad3_ Net-_U13-Pad3_ Net-_U23-Pad3_ d_or +U40 Net-_U36-Pad3_ Net-_U37-Pad2_ inhibit_out_dig d_or +U42 Net-_U33-Pad2_ out_bar_dig d_inverter +U36 inhibit_in_dig Qa_bar Net-_U36-Pad3_ d_or +U37 Net-_U29-Pad3_ Net-_U37-Pad2_ d_inverter +U11 Adig Qd_bar Net-_U11-Pad3_ d_and +U29 Net-_U26-Pad3_ Qd_bar Net-_U29-Pad3_ d_and +U15 Net-_U10-Pad3_ Qc Net-_U15-Pad3_ d_and +U22 Qb Net-_U17-Pad3_ Net-_U22-Pad3_ d_and +.end diff --git a/library/SubcircuitLibrary/CD4089B/CD4089B.cir.out b/library/SubcircuitLibrary/CD4089B/CD4089B.cir.out new file mode 100644 index 000000000..1e6966342 --- /dev/null +++ b/library/SubcircuitLibrary/CD4089B/CD4089B.cir.out @@ -0,0 +1,168 @@ +.title kicad schematic + +* u7 net-_u16-pad1_ qa_bar set_dig reset_dig qb qb_bar d_tff +* u6 net-_u16-pad1_ clk_dig set_dig reset_dig qa qa_bar d_tff +* u2 gnd net-_u2-pad2_ adc_bridge_1 +* u5 net-_u2-pad2_ net-_u16-pad1_ d_inverter +* u16 net-_u16-pad1_ qc_bar set_dig reset_dig qd qd_bar d_tff +* u8 net-_u16-pad1_ qb_bar set_dig reset_dig qc qc_bar d_tff +* u12 cdig qb_bar net-_u12-pad3_ d_and +* u14 net-_u14-pad1_ qc net-_u14-pad3_ d_and +* u21 qb net-_u15-pad3_ i_dig d_and +* u10 qd qa net-_u10-pad3_ d_and +* u13 ddig qa_bar net-_u13-pad3_ d_and +* u18 net-_u12-pad3_ qa net-_u18-pad3_ d_and +* u9 bdig qa net-_u14-pad1_ d_and +* u1 i_dig cdig ddig set_dig out_bar_dig out_dig inhibit_out_dig unconnected-_u1-pad8_ clk_dig strobe_dig inhibit_in_dig cascade_dig reset_dig adig bdig unconnected-_u1-pad16_ port +* u38 net-_u34-pad2_ net-_u35-pad3_ net-_u38-pad3_ d_and +* u34 strobe_dig net-_u34-pad2_ d_inverter +* u33 cascade_dig net-_u33-pad2_ out_dig d_or +* u41 net-_u38-pad3_ net-_u39-pad2_ net-_u33-pad2_ d_and +* u39 inhibit_in_dig net-_u39-pad2_ d_inverter +* u35 net-_u28-pad2_ net-_u27-pad3_ net-_u35-pad3_ d_and +* u30 out_dig out dac_bridge_1 +* u32 i_dig 15_out dac_bridge_1 +* u31 out_bar_dig out_bar dac_bridge_1 +* u43 inhibit_out_dig inhibit_out dac_bridge_1 +* u17 net-_u11-pad3_ qc net-_u17-pad3_ d_and +* u20 qb net-_u14-pad3_ net-_u20-pad3_ d_and +* u25 net-_u20-pad3_ net-_u23-pad3_ net-_u25-pad3_ d_or +* u24 net-_u22-pad3_ qa net-_u24-pad3_ d_and +* u28 clk_dig net-_u28-pad2_ d_inverter +* u27 net-_u24-pad3_ net-_u25-pad3_ net-_u27-pad3_ d_or +* u26 qb_bar qc_bar net-_u26-pad3_ d_and +* u23 net-_u18-pad3_ net-_u13-pad3_ net-_u23-pad3_ d_or +* u40 net-_u36-pad3_ net-_u37-pad2_ inhibit_out_dig d_or +* u42 net-_u33-pad2_ out_bar_dig d_inverter +* u36 inhibit_in_dig qa_bar net-_u36-pad3_ d_or +* u37 net-_u29-pad3_ net-_u37-pad2_ d_inverter +* u11 adig qd_bar net-_u11-pad3_ d_and +* u29 net-_u26-pad3_ qd_bar net-_u29-pad3_ d_and +* u15 net-_u10-pad3_ qc net-_u15-pad3_ d_and +* u22 qb net-_u17-pad3_ net-_u22-pad3_ d_and +a1 net-_u16-pad1_ qa_bar set_dig reset_dig qb qb_bar u7 +a2 net-_u16-pad1_ clk_dig set_dig reset_dig qa qa_bar u6 +a3 [gnd ] [net-_u2-pad2_ ] u2 +a4 net-_u2-pad2_ net-_u16-pad1_ u5 +a5 net-_u16-pad1_ qc_bar set_dig reset_dig qd qd_bar u16 +a6 net-_u16-pad1_ qb_bar set_dig reset_dig qc qc_bar u8 +a7 [cdig qb_bar ] net-_u12-pad3_ u12 +a8 [net-_u14-pad1_ qc ] net-_u14-pad3_ u14 +a9 [qb net-_u15-pad3_ ] i_dig u21 +a10 [qd qa ] net-_u10-pad3_ u10 +a11 [ddig qa_bar ] net-_u13-pad3_ u13 +a12 [net-_u12-pad3_ qa ] net-_u18-pad3_ u18 +a13 [bdig qa ] net-_u14-pad1_ u9 +a14 [net-_u34-pad2_ net-_u35-pad3_ ] net-_u38-pad3_ u38 +a15 strobe_dig net-_u34-pad2_ u34 +a16 [cascade_dig net-_u33-pad2_ ] out_dig u33 +a17 [net-_u38-pad3_ net-_u39-pad2_ ] net-_u33-pad2_ u41 +a18 inhibit_in_dig net-_u39-pad2_ u39 +a19 [net-_u28-pad2_ net-_u27-pad3_ ] net-_u35-pad3_ u35 +a20 [out_dig ] [out ] u30 +a21 [i_dig ] [15_out ] u32 +a22 [out_bar_dig ] [out_bar ] u31 +a23 [inhibit_out_dig ] [inhibit_out ] u43 +a24 [net-_u11-pad3_ qc ] net-_u17-pad3_ u17 +a25 [qb net-_u14-pad3_ ] net-_u20-pad3_ u20 +a26 [net-_u20-pad3_ net-_u23-pad3_ ] net-_u25-pad3_ u25 +a27 [net-_u22-pad3_ qa ] net-_u24-pad3_ u24 +a28 clk_dig net-_u28-pad2_ u28 +a29 [net-_u24-pad3_ net-_u25-pad3_ ] net-_u27-pad3_ u27 +a30 [qb_bar qc_bar ] net-_u26-pad3_ u26 +a31 [net-_u18-pad3_ net-_u13-pad3_ ] net-_u23-pad3_ u23 +a32 [net-_u36-pad3_ net-_u37-pad2_ ] inhibit_out_dig u40 +a33 net-_u33-pad2_ out_bar_dig u42 +a34 [inhibit_in_dig qa_bar ] net-_u36-pad3_ u36 +a35 net-_u29-pad3_ net-_u37-pad2_ u37 +a36 [adig qd_bar ] net-_u11-pad3_ u11 +a37 [net-_u26-pad3_ qd_bar ] net-_u29-pad3_ u29 +a38 [net-_u10-pad3_ qc ] net-_u15-pad3_ u15 +a39 [qb net-_u17-pad3_ ] net-_u22-pad3_ u22 +* Schematic Name: d_tff, Ngspice Name: d_tff +.model u7 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tff, Ngspice Name: d_tff +.model u6 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tff, Ngspice Name: d_tff +.model u16 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tff, Ngspice Name: d_tff +.model u8 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u33 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u41 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u39 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u35 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u30 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u32 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u31 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u43 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u25 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u27 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u23 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u40 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u42 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u36 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4089B/CD4089B.kicad_sch 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"/f2e8fb61-0b04-4c41-9fe2-08cc096a5b6a" + (reference "U32") (unit 1) (value "dac_bridge_1") (footprint "") + ) + (path "/8892e774-9fd3-4bed-bed5-4b9420e76645" + (reference "U33") (unit 1) (value "d_or") (footprint "") + ) + (path "/84974a3f-cb2f-4490-9d66-b2912db2a9f6" + (reference "U34") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/59e5fd2d-8758-4784-9199-88a03c41980b" + (reference "U35") (unit 1) (value "d_and") (footprint "") + ) + (path "/0ea077e0-e0f0-4ca7-b594-b9196dba8dd2" + (reference "U36") (unit 1) (value "d_or") (footprint "") + ) + (path "/241a4d12-e3be-4b4a-96d9-7974c5a0aad6" + (reference "U37") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/0016021a-b185-45a7-ad48-98b943f1532e" + (reference "U38") (unit 1) (value "d_and") (footprint "") + ) + (path "/45d92d7e-f6d5-4597-9eb3-68171b5eef98" + (reference "U39") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/f43599f9-5639-4790-aa5b-dda1c5af7569" + (reference "U40") (unit 1) (value "d_or") (footprint "") + ) + (path "/1455402e-fd68-4c54-bca1-f3ad822989f1" + (reference "U41") (unit 1) (value "d_and") (footprint "") + ) + (path "/2fe54405-665a-4a68-a8bb-fc06b542d74d" + (reference "U42") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/ac6028c8-5848-4415-aab1-6d504381aa60" + (reference "U43") (unit 1) (value "dac_bridge_1") (footprint "") + ) + ) +) diff --git a/library/SubcircuitLibrary/CD4089B/CD4089B.sub b/library/SubcircuitLibrary/CD4089B/CD4089B.sub new file mode 100644 index 000000000..a9d880a81 --- /dev/null +++ b/library/SubcircuitLibrary/CD4089B/CD4089B.sub @@ -0,0 +1,162 @@ +* Subcircuit CD4089B +.subckt CD4089B i_dig cdig ddig set_dig out_bar_dig out_dig inhibit_out_dig unconnected-_u1-pad8_ clk_dig strobe_dig inhibit_in_dig cascade_dig reset_dig adig bdig unconnected-_u1-pad16_ +.title kicad schematic +* u7 net-_u16-pad1_ qa_bar set_dig reset_dig qb qb_bar d_tff +* u6 net-_u16-pad1_ clk_dig set_dig reset_dig qa qa_bar d_tff +* u2 gnd net-_u2-pad2_ adc_bridge_1 +* u5 net-_u2-pad2_ net-_u16-pad1_ d_inverter +* u16 net-_u16-pad1_ qc_bar set_dig reset_dig qd qd_bar d_tff +* u8 net-_u16-pad1_ qb_bar set_dig reset_dig qc qc_bar d_tff +* u12 cdig qb_bar net-_u12-pad3_ d_and +* u14 net-_u14-pad1_ qc net-_u14-pad3_ d_and +* u21 qb net-_u15-pad3_ i_dig d_and +* u10 qd qa net-_u10-pad3_ d_and +* u13 ddig qa_bar net-_u13-pad3_ d_and +* u18 net-_u12-pad3_ qa net-_u18-pad3_ d_and +* u9 bdig qa net-_u14-pad1_ d_and +* u38 net-_u34-pad2_ net-_u35-pad3_ net-_u38-pad3_ d_and +* u34 strobe_dig net-_u34-pad2_ d_inverter +* u33 cascade_dig net-_u33-pad2_ out_dig d_or +* u41 net-_u38-pad3_ net-_u39-pad2_ net-_u33-pad2_ d_and +* u39 inhibit_in_dig net-_u39-pad2_ d_inverter +* u35 net-_u28-pad2_ net-_u27-pad3_ net-_u35-pad3_ d_and +* u30 out_dig out dac_bridge_1 +* u32 i_dig 15_out dac_bridge_1 +* u31 out_bar_dig out_bar dac_bridge_1 +* u43 inhibit_out_dig inhibit_out dac_bridge_1 +* u17 net-_u11-pad3_ qc net-_u17-pad3_ d_and +* u20 qb net-_u14-pad3_ net-_u20-pad3_ d_and +* u25 net-_u20-pad3_ net-_u23-pad3_ net-_u25-pad3_ d_or +* u24 net-_u22-pad3_ qa net-_u24-pad3_ d_and +* u28 clk_dig net-_u28-pad2_ d_inverter +* u27 net-_u24-pad3_ net-_u25-pad3_ net-_u27-pad3_ d_or +* u26 qb_bar qc_bar net-_u26-pad3_ d_and +* u23 net-_u18-pad3_ net-_u13-pad3_ net-_u23-pad3_ d_or +* u40 net-_u36-pad3_ net-_u37-pad2_ inhibit_out_dig d_or +* u42 net-_u33-pad2_ out_bar_dig d_inverter +* u36 inhibit_in_dig qa_bar net-_u36-pad3_ d_or +* u37 net-_u29-pad3_ net-_u37-pad2_ d_inverter +* u11 adig qd_bar net-_u11-pad3_ d_and +* u29 net-_u26-pad3_ qd_bar net-_u29-pad3_ d_and +* u15 net-_u10-pad3_ qc net-_u15-pad3_ d_and +* u22 qb net-_u17-pad3_ net-_u22-pad3_ d_and +a1 net-_u16-pad1_ qa_bar set_dig reset_dig qb qb_bar u7 +a2 net-_u16-pad1_ clk_dig set_dig reset_dig qa qa_bar u6 +a3 [gnd ] [net-_u2-pad2_ ] u2 +a4 net-_u2-pad2_ net-_u16-pad1_ u5 +a5 net-_u16-pad1_ qc_bar set_dig reset_dig qd qd_bar u16 +a6 net-_u16-pad1_ qb_bar set_dig reset_dig qc qc_bar u8 +a7 [cdig qb_bar ] net-_u12-pad3_ u12 +a8 [net-_u14-pad1_ qc ] net-_u14-pad3_ u14 +a9 [qb net-_u15-pad3_ ] i_dig u21 +a10 [qd qa ] net-_u10-pad3_ u10 +a11 [ddig qa_bar ] net-_u13-pad3_ u13 +a12 [net-_u12-pad3_ qa ] net-_u18-pad3_ u18 +a13 [bdig qa ] net-_u14-pad1_ u9 +a14 [net-_u34-pad2_ net-_u35-pad3_ ] net-_u38-pad3_ u38 +a15 strobe_dig net-_u34-pad2_ u34 +a16 [cascade_dig net-_u33-pad2_ ] out_dig u33 +a17 [net-_u38-pad3_ net-_u39-pad2_ ] net-_u33-pad2_ u41 +a18 inhibit_in_dig net-_u39-pad2_ u39 +a19 [net-_u28-pad2_ net-_u27-pad3_ ] net-_u35-pad3_ u35 +a20 [out_dig ] [out ] u30 +a21 [i_dig ] [15_out ] u32 +a22 [out_bar_dig ] [out_bar ] u31 +a23 [inhibit_out_dig ] [inhibit_out ] u43 +a24 [net-_u11-pad3_ qc ] net-_u17-pad3_ u17 +a25 [qb net-_u14-pad3_ ] net-_u20-pad3_ u20 +a26 [net-_u20-pad3_ net-_u23-pad3_ ] net-_u25-pad3_ u25 +a27 [net-_u22-pad3_ qa ] net-_u24-pad3_ u24 +a28 clk_dig net-_u28-pad2_ u28 +a29 [net-_u24-pad3_ net-_u25-pad3_ ] net-_u27-pad3_ u27 +a30 [qb_bar qc_bar ] net-_u26-pad3_ u26 +a31 [net-_u18-pad3_ net-_u13-pad3_ ] net-_u23-pad3_ u23 +a32 [net-_u36-pad3_ net-_u37-pad2_ ] inhibit_out_dig u40 +a33 net-_u33-pad2_ out_bar_dig u42 +a34 [inhibit_in_dig qa_bar ] net-_u36-pad3_ u36 +a35 net-_u29-pad3_ net-_u37-pad2_ u37 +a36 [adig qd_bar ] net-_u11-pad3_ u11 +a37 [net-_u26-pad3_ qd_bar ] net-_u29-pad3_ u29 +a38 [net-_u10-pad3_ qc ] net-_u15-pad3_ u15 +a39 [qb net-_u17-pad3_ ] net-_u22-pad3_ u22 +* Schematic Name: d_tff, Ngspice Name: d_tff +.model u7 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tff, Ngspice Name: d_tff +.model u6 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_tff, Ngspice Name: d_tff +.model u16 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tff, Ngspice Name: d_tff +.model u8 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u33 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u41 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u39 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u35 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u30 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u32 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u31 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u43 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u25 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u27 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u23 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u40 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u42 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u36 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends CD4089B \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4089B/CD4089B_Previous_Values.xml b/library/SubcircuitLibrary/CD4089B/CD4089B_Previous_Values.xml new file mode 100644 index 000000000..b259e3c2d --- /dev/null +++ b/library/SubcircuitLibrary/CD4089B/CD4089B_Previous_Values.xml @@ -0,0 +1 @@ +d_ord_ordac_bridgedac_bridgedac_bridgedac_bridged_andd_ord_inverterd_andd_ord_ord_andd_inverterd_andd_andd_ord_inverterd_inverterd_andd_inverterd_andd_andd_andd_andd_andd_andd_andd_andd_andd_inverteradc_bridgeadc_bridgeadc_bridgeadc_bridged_tff1.0e-9d_tff1.0e-9d_tff1.0e-9d_tff1.0e-9d_andd_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4089B/analysis b/library/SubcircuitLibrary/CD4089B/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/CD4089B/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4099B/CD4099B.cir b/library/SubcircuitLibrary/CD4099B/CD4099B.cir new file mode 100644 index 000000000..c95a47182 --- /dev/null +++ b/library/SubcircuitLibrary/CD4099B/CD4099B.cir @@ -0,0 +1,40 @@ +.title KiCad schematic +U3 Data Net-_U15-Pad3_ Net-_U2-Pad3_ Net-_U14-Pad3_ Q3 unconnected-_U3-Pad6_ d_dlatch +U7 Data Net-_U12-Pad3_ Net-_U2-Pad3_ Net-_U14-Pad3_ Q2 unconnected-_U7-Pad6_ d_dlatch +U6 Data Net-_U10-Pad3_ Net-_U2-Pad3_ Net-_U14-Pad3_ Q0 unconnected-_U6-Pad6_ d_dlatch +U8 Data Net-_U13-Pad3_ Net-_U2-Pad3_ Net-_U14-Pad3_ Q6 unconnected-_U8-Pad6_ d_dlatch +U9 Data Net-_U17-Pad3_ Net-_U2-Pad3_ Net-_U14-Pad3_ Q4 unconnected-_U9-Pad6_ d_dlatch +U1 Q7 Reset Data Write_Disable A0 A1 A2 unconnected-_U1-Pad8_ Q0 Q1 Q2 Q3 Q4 Q5 Q6 unconnected-_U1-Pad16_ PORT +U2 Data Net-_U11-Pad3_ Net-_U2-Pad3_ Net-_U14-Pad3_ Q1 unconnected-_U2-Pad6_ d_dlatch +U5 Data Net-_U16-Pad3_ Net-_U2-Pad3_ Net-_U14-Pad3_ Q7 unconnected-_U5-Pad6_ d_dlatch +U4 Data Net-_U18-Pad3_ Net-_U2-Pad3_ Net-_U14-Pad3_ Q5 unconnected-_U4-Pad6_ d_dlatch +U11 Net-_U10-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_and +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and +U14 Reset Write_Disable Net-_U14-Pad3_ d_and +U19 Write_Disable Net-_U10-Pad1_ d_inverter +U25 Net-_U25-Pad1_ A0 Net-_U18-Pad2_ d_and +U24 Net-_U24-Pad1_ Net-_U24-Pad2_ Net-_U17-Pad2_ d_and +U26 Net-_U26-Pad1_ Net-_U24-Pad2_ Net-_U13-Pad2_ d_and +U27 Net-_U27-Pad1_ A0 Net-_U16-Pad2_ d_and +U35 A2 A1 Net-_U27-Pad1_ d_and +U33 A2 Net-_U20-Pad2_ Net-_U25-Pad1_ d_and +U34 A2 A1 Net-_U26-Pad1_ d_and +U36 A2 Net-_U21-Pad2_ d_inverter +U38 A0 Net-_U24-Pad2_ d_inverter +U37 A1 Net-_U20-Pad2_ d_inverter +U32 A2 Net-_U20-Pad2_ Net-_U24-Pad1_ d_and +U29 A1 Net-_U24-Pad2_ Net-_U21-Pad1_ d_and +U30 A1 A0 Net-_U22-Pad1_ d_and +U31 Net-_U24-Pad2_ Net-_U20-Pad2_ Net-_U23-Pad1_ d_and +U28 A0 Net-_U21-Pad2_ Net-_U20-Pad1_ d_and +U23 Net-_U23-Pad1_ Net-_U21-Pad2_ Net-_U10-Pad2_ d_and +U20 Net-_U20-Pad1_ Net-_U20-Pad2_ Net-_U11-Pad2_ d_and +U22 Net-_U22-Pad1_ Net-_U21-Pad2_ Net-_U15-Pad2_ d_and +U21 Net-_U21-Pad1_ Net-_U21-Pad2_ Net-_U12-Pad2_ d_and +U12 Net-_U10-Pad1_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_and +U15 Net-_U10-Pad1_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_and +U18 Net-_U10-Pad1_ Net-_U18-Pad2_ Net-_U18-Pad3_ d_and +U13 Net-_U10-Pad1_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_and +U16 Net-_U10-Pad1_ Net-_U16-Pad2_ Net-_U16-Pad3_ d_and +U17 Net-_U10-Pad1_ Net-_U17-Pad2_ Net-_U17-Pad3_ d_and +.end diff --git a/library/SubcircuitLibrary/CD4099B/CD4099B.cir.out b/library/SubcircuitLibrary/CD4099B/CD4099B.cir.out new file mode 100644 index 000000000..155a2c4df --- /dev/null +++ b/library/SubcircuitLibrary/CD4099B/CD4099B.cir.out @@ -0,0 +1,160 @@ +.title kicad schematic + +* u3 data net-_u15-pad3_ net-_u2-pad3_ net-_u14-pad3_ q3 unconnected-_u3-pad6_ d_dlatch +* u7 data net-_u12-pad3_ net-_u2-pad3_ net-_u14-pad3_ q2 unconnected-_u7-pad6_ d_dlatch +* u6 data net-_u10-pad3_ net-_u2-pad3_ net-_u14-pad3_ q0 unconnected-_u6-pad6_ d_dlatch +* u8 data net-_u13-pad3_ net-_u2-pad3_ net-_u14-pad3_ q6 unconnected-_u8-pad6_ d_dlatch +* u9 data net-_u17-pad3_ net-_u2-pad3_ net-_u14-pad3_ q4 unconnected-_u9-pad6_ d_dlatch +* u1 q7 reset data write_disable a0 a1 a2 unconnected-_u1-pad8_ q0 q1 q2 q3 q4 q5 q6 unconnected-_u1-pad16_ port +* u2 data net-_u11-pad3_ net-_u2-pad3_ net-_u14-pad3_ q1 unconnected-_u2-pad6_ d_dlatch +* u5 data net-_u16-pad3_ net-_u2-pad3_ net-_u14-pad3_ q7 unconnected-_u5-pad6_ d_dlatch +* u4 data net-_u18-pad3_ net-_u2-pad3_ net-_u14-pad3_ q5 unconnected-_u4-pad6_ d_dlatch +* u11 net-_u10-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u14 reset write_disable net-_u14-pad3_ d_and +* u19 write_disable net-_u10-pad1_ d_inverter +* u25 net-_u25-pad1_ a0 net-_u18-pad2_ d_and +* u24 net-_u24-pad1_ net-_u24-pad2_ net-_u17-pad2_ d_and +* u26 net-_u26-pad1_ net-_u24-pad2_ net-_u13-pad2_ d_and +* u27 net-_u27-pad1_ a0 net-_u16-pad2_ d_and +* u35 a2 a1 net-_u27-pad1_ d_and +* u33 a2 net-_u20-pad2_ net-_u25-pad1_ d_and +* u34 a2 a1 net-_u26-pad1_ d_and +* u36 a2 net-_u21-pad2_ d_inverter +* u38 a0 net-_u24-pad2_ d_inverter +* u37 a1 net-_u20-pad2_ d_inverter +* u32 a2 net-_u20-pad2_ net-_u24-pad1_ d_and +* u29 a1 net-_u24-pad2_ net-_u21-pad1_ d_and +* u30 a1 a0 net-_u22-pad1_ d_and +* u31 net-_u24-pad2_ net-_u20-pad2_ net-_u23-pad1_ d_and +* u28 a0 net-_u21-pad2_ net-_u20-pad1_ d_and +* u23 net-_u23-pad1_ net-_u21-pad2_ net-_u10-pad2_ d_and +* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u11-pad2_ d_and +* u22 net-_u22-pad1_ net-_u21-pad2_ net-_u15-pad2_ d_and +* u21 net-_u21-pad1_ net-_u21-pad2_ net-_u12-pad2_ d_and +* u12 net-_u10-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_and +* u15 net-_u10-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_and +* u18 net-_u10-pad1_ net-_u18-pad2_ net-_u18-pad3_ d_and +* u13 net-_u10-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_and +* u16 net-_u10-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_and +* u17 net-_u10-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_and +a1 data net-_u15-pad3_ net-_u2-pad3_ net-_u14-pad3_ q3 unconnected-_u3-pad6_ u3 +a2 data net-_u12-pad3_ net-_u2-pad3_ net-_u14-pad3_ q2 unconnected-_u7-pad6_ u7 +a3 data net-_u10-pad3_ net-_u2-pad3_ net-_u14-pad3_ q0 unconnected-_u6-pad6_ u6 +a4 data net-_u13-pad3_ net-_u2-pad3_ net-_u14-pad3_ q6 unconnected-_u8-pad6_ u8 +a5 data net-_u17-pad3_ net-_u2-pad3_ net-_u14-pad3_ q4 unconnected-_u9-pad6_ u9 +a6 data net-_u11-pad3_ net-_u2-pad3_ net-_u14-pad3_ q1 unconnected-_u2-pad6_ u2 +a7 data net-_u16-pad3_ net-_u2-pad3_ net-_u14-pad3_ q7 unconnected-_u5-pad6_ u5 +a8 data net-_u18-pad3_ net-_u2-pad3_ net-_u14-pad3_ q5 unconnected-_u4-pad6_ u4 +a9 [net-_u10-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a10 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a11 [reset write_disable ] net-_u14-pad3_ u14 +a12 write_disable net-_u10-pad1_ u19 +a13 [net-_u25-pad1_ a0 ] net-_u18-pad2_ u25 +a14 [net-_u24-pad1_ net-_u24-pad2_ ] net-_u17-pad2_ u24 +a15 [net-_u26-pad1_ net-_u24-pad2_ ] net-_u13-pad2_ u26 +a16 [net-_u27-pad1_ a0 ] net-_u16-pad2_ u27 +a17 [a2 a1 ] net-_u27-pad1_ u35 +a18 [a2 net-_u20-pad2_ ] net-_u25-pad1_ u33 +a19 [a2 a1 ] net-_u26-pad1_ u34 +a20 a2 net-_u21-pad2_ u36 +a21 a0 net-_u24-pad2_ u38 +a22 a1 net-_u20-pad2_ u37 +a23 [a2 net-_u20-pad2_ ] net-_u24-pad1_ u32 +a24 [a1 net-_u24-pad2_ ] net-_u21-pad1_ u29 +a25 [a1 a0 ] net-_u22-pad1_ u30 +a26 [net-_u24-pad2_ net-_u20-pad2_ ] net-_u23-pad1_ u31 +a27 [a0 net-_u21-pad2_ ] net-_u20-pad1_ u28 +a28 [net-_u23-pad1_ net-_u21-pad2_ ] net-_u10-pad2_ u23 +a29 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u11-pad2_ u20 +a30 [net-_u22-pad1_ net-_u21-pad2_ ] net-_u15-pad2_ u22 +a31 [net-_u21-pad1_ net-_u21-pad2_ ] net-_u12-pad2_ u21 +a32 [net-_u10-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a33 [net-_u10-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a34 [net-_u10-pad1_ net-_u18-pad2_ ] net-_u18-pad3_ u18 +a35 [net-_u10-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a36 [net-_u10-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16 +a37 [net-_u10-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17 +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u3 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u7 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u6 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u8 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u9 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u2 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u5 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u4 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u35 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u38 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4099B/CD4099B.kicad_sch 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(footprint "") + ) + (path "/fc0f0ae1-7944-42b3-9da6-25c8c02a03e2" + (reference "U28") (unit 1) (value "d_and") (footprint "") + ) + (path "/e7f05363-d313-4b4e-bde8-58c8767ea946" + (reference "U29") (unit 1) (value "d_and") (footprint "") + ) + (path "/8f28c24a-505f-43f8-9c6b-8f6989986127" + (reference "U30") (unit 1) (value "d_and") (footprint "") + ) + (path "/d67410c1-129a-4137-b069-29db41c27de8" + (reference "U31") (unit 1) (value "d_and") (footprint "") + ) + (path "/a47bbcf7-082a-416d-b977-5b68a8691ce9" + (reference "U32") (unit 1) (value "d_and") (footprint "") + ) + (path "/44dad8aa-f812-401e-9957-7c958f6983ed" + (reference "U33") (unit 1) (value "d_and") (footprint "") + ) + (path "/582d841d-8e3c-4280-84e9-9212bc51d25d" + (reference "U34") (unit 1) (value "d_and") (footprint "") + ) + (path "/9be4deb9-f5a5-4b57-a839-a610b0b64e52" + (reference "U35") (unit 1) (value "d_and") (footprint "") + ) + (path "/350f61e8-c51d-46a1-ae31-571988189c76" + (reference "U36") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/eb2156fa-61db-4a9a-a995-dc9cf1bb0563" + (reference "U37") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/562f7345-9519-4eeb-993e-aaad57e1dfa0" + (reference "U38") (unit 1) (value "d_inverter") (footprint "") + ) + ) +) diff --git a/library/SubcircuitLibrary/CD4099B/CD4099B.sub b/library/SubcircuitLibrary/CD4099B/CD4099B.sub new file mode 100644 index 000000000..e66d59a33 --- /dev/null +++ b/library/SubcircuitLibrary/CD4099B/CD4099B.sub @@ -0,0 +1,154 @@ +* Subcircuit CD4099B +.subckt CD4099B q7 reset data write_disable a0 a1 a2 unconnected-_u1-pad8_ q0 q1 q2 q3 q4 q5 q6 unconnected-_u1-pad16_ +.title kicad schematic +* u3 data net-_u15-pad3_ net-_u2-pad3_ net-_u14-pad3_ q3 unconnected-_u3-pad6_ d_dlatch +* u7 data net-_u12-pad3_ net-_u2-pad3_ net-_u14-pad3_ q2 unconnected-_u7-pad6_ d_dlatch +* u6 data net-_u10-pad3_ net-_u2-pad3_ net-_u14-pad3_ q0 unconnected-_u6-pad6_ d_dlatch +* u8 data net-_u13-pad3_ net-_u2-pad3_ net-_u14-pad3_ q6 unconnected-_u8-pad6_ d_dlatch +* u9 data net-_u17-pad3_ net-_u2-pad3_ net-_u14-pad3_ q4 unconnected-_u9-pad6_ d_dlatch +* u2 data net-_u11-pad3_ net-_u2-pad3_ net-_u14-pad3_ q1 unconnected-_u2-pad6_ d_dlatch +* u5 data net-_u16-pad3_ net-_u2-pad3_ net-_u14-pad3_ q7 unconnected-_u5-pad6_ d_dlatch +* u4 data net-_u18-pad3_ net-_u2-pad3_ net-_u14-pad3_ q5 unconnected-_u4-pad6_ d_dlatch +* u11 net-_u10-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u14 reset write_disable net-_u14-pad3_ d_and +* u19 write_disable net-_u10-pad1_ d_inverter +* u25 net-_u25-pad1_ a0 net-_u18-pad2_ d_and +* u24 net-_u24-pad1_ net-_u24-pad2_ net-_u17-pad2_ d_and +* u26 net-_u26-pad1_ net-_u24-pad2_ net-_u13-pad2_ d_and +* u27 net-_u27-pad1_ a0 net-_u16-pad2_ d_and +* u35 a2 a1 net-_u27-pad1_ d_and +* u33 a2 net-_u20-pad2_ net-_u25-pad1_ d_and +* u34 a2 a1 net-_u26-pad1_ d_and +* u36 a2 net-_u21-pad2_ d_inverter +* u38 a0 net-_u24-pad2_ d_inverter +* u37 a1 net-_u20-pad2_ d_inverter +* u32 a2 net-_u20-pad2_ net-_u24-pad1_ d_and +* u29 a1 net-_u24-pad2_ net-_u21-pad1_ d_and +* u30 a1 a0 net-_u22-pad1_ d_and +* u31 net-_u24-pad2_ net-_u20-pad2_ net-_u23-pad1_ d_and +* u28 a0 net-_u21-pad2_ net-_u20-pad1_ d_and +* u23 net-_u23-pad1_ net-_u21-pad2_ net-_u10-pad2_ d_and +* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u11-pad2_ d_and +* u22 net-_u22-pad1_ net-_u21-pad2_ net-_u15-pad2_ d_and +* u21 net-_u21-pad1_ net-_u21-pad2_ net-_u12-pad2_ d_and +* u12 net-_u10-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_and +* u15 net-_u10-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_and +* u18 net-_u10-pad1_ net-_u18-pad2_ net-_u18-pad3_ d_and +* u13 net-_u10-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_and +* u16 net-_u10-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_and +* u17 net-_u10-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_and +a1 data net-_u15-pad3_ net-_u2-pad3_ net-_u14-pad3_ q3 unconnected-_u3-pad6_ u3 +a2 data net-_u12-pad3_ net-_u2-pad3_ net-_u14-pad3_ q2 unconnected-_u7-pad6_ u7 +a3 data net-_u10-pad3_ net-_u2-pad3_ net-_u14-pad3_ q0 unconnected-_u6-pad6_ u6 +a4 data net-_u13-pad3_ net-_u2-pad3_ net-_u14-pad3_ q6 unconnected-_u8-pad6_ u8 +a5 data net-_u17-pad3_ net-_u2-pad3_ net-_u14-pad3_ q4 unconnected-_u9-pad6_ u9 +a6 data net-_u11-pad3_ net-_u2-pad3_ net-_u14-pad3_ q1 unconnected-_u2-pad6_ u2 +a7 data net-_u16-pad3_ net-_u2-pad3_ net-_u14-pad3_ q7 unconnected-_u5-pad6_ u5 +a8 data net-_u18-pad3_ net-_u2-pad3_ net-_u14-pad3_ q5 unconnected-_u4-pad6_ u4 +a9 [net-_u10-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a10 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a11 [reset write_disable ] net-_u14-pad3_ u14 +a12 write_disable net-_u10-pad1_ u19 +a13 [net-_u25-pad1_ a0 ] net-_u18-pad2_ u25 +a14 [net-_u24-pad1_ net-_u24-pad2_ ] net-_u17-pad2_ u24 +a15 [net-_u26-pad1_ net-_u24-pad2_ ] net-_u13-pad2_ u26 +a16 [net-_u27-pad1_ a0 ] net-_u16-pad2_ u27 +a17 [a2 a1 ] net-_u27-pad1_ u35 +a18 [a2 net-_u20-pad2_ ] net-_u25-pad1_ u33 +a19 [a2 a1 ] net-_u26-pad1_ u34 +a20 a2 net-_u21-pad2_ u36 +a21 a0 net-_u24-pad2_ u38 +a22 a1 net-_u20-pad2_ u37 +a23 [a2 net-_u20-pad2_ ] net-_u24-pad1_ u32 +a24 [a1 net-_u24-pad2_ ] net-_u21-pad1_ u29 +a25 [a1 a0 ] net-_u22-pad1_ u30 +a26 [net-_u24-pad2_ net-_u20-pad2_ ] net-_u23-pad1_ u31 +a27 [a0 net-_u21-pad2_ ] net-_u20-pad1_ u28 +a28 [net-_u23-pad1_ net-_u21-pad2_ ] net-_u10-pad2_ u23 +a29 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u11-pad2_ u20 +a30 [net-_u22-pad1_ net-_u21-pad2_ ] net-_u15-pad2_ u22 +a31 [net-_u21-pad1_ net-_u21-pad2_ ] net-_u12-pad2_ u21 +a32 [net-_u10-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a33 [net-_u10-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a34 [net-_u10-pad1_ net-_u18-pad2_ ] net-_u18-pad3_ u18 +a35 [net-_u10-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a36 [net-_u10-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16 +a37 [net-_u10-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17 +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u3 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u7 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u6 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u8 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u9 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u2 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u5 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u4 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u35 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u38 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends CD4099B \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4099B/CD4099B_Previous_Values.xml b/library/SubcircuitLibrary/CD4099B/CD4099B_Previous_Values.xml new file mode 100644 index 000000000..e12e4cdab --- /dev/null +++ b/library/SubcircuitLibrary/CD4099B/CD4099B_Previous_Values.xml @@ -0,0 +1 @@ +d_dlatch1.0e-9d_dlatch1.0e-9d_dlatch1.0e-9d_dlatch1.0e-9d_dlatch1.0e-9d_dlatch1.0e-9d_dlatch1.0e-9d_dlatch1.0e-9d_andd_andd_andd_inverterd_andd_andd_andd_andd_andd_andd_andd_inverterd_inverterd_inverterd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4099B/analysis b/library/SubcircuitLibrary/CD4099B/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/CD4099B/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/L298N/#auto_saved_files# b/library/SubcircuitLibrary/L298N/#auto_saved_files# new file mode 100644 index 000000000..8f414146d --- /dev/null +++ b/library/SubcircuitLibrary/L298N/#auto_saved_files# @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\SubcircuitLibrary\L298N\_autosave-L298N.sch diff --git a/library/SubcircuitLibrary/L298N/L298N.cir b/library/SubcircuitLibrary/L298N/L298N.cir new file mode 100644 index 000000000..6ee55d65a --- /dev/null +++ b/library/SubcircuitLibrary/L298N/L298N.cir @@ -0,0 +1,37 @@ +.title KiCad schematic +U1 GND out1 out2 vdd INPUT1 EnA INPUT2 GND unconnected-_U1-Pad9_ INPUT3 EnB INPUT4 out3 out4 GND PORT +Q2 out1 Net-_U13-Pad2_ GND eSim_NPN +Q5 out2 Net-_U17-Pad2_ vdd eSim_PNP +Q1 out1 Net-_U12-Pad2_ vdd eSim_PNP +Q6 out2 Net-_U16-Pad2_ GND eSim_NPN +U14 Net-_U10-Pad3_ Net-_U14-Pad2_ dac_bridge_1 +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_nand +Q7 out4 Net-_U19-Pad2_ vdd eSim_PNP +Q3 out3 Net-_U14-Pad2_ vdd eSim_PNP +U27 INPUT4 Net-_U22-Pad1_ adc_bridge_1 +U25 Net-_U22-Pad1_ Net-_U23-Pad1_ d_inverter +U26 INPUT2 Net-_U20-Pad1_ adc_bridge_1 +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ dac_bridge_1 +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ dac_bridge_1 +U6 Net-_U2-Pad2_ Net-_U6-Pad2_ d_inverter +U8 Net-_U2-Pad2_ Net-_U20-Pad2_ Net-_U12-Pad1_ d_nand +U9 Net-_U6-Pad2_ Net-_U20-Pad2_ Net-_U13-Pad1_ d_and +U4 EnA Net-_U20-Pad2_ adc_bridge_1 +U22 Net-_U22-Pad1_ Net-_U10-Pad2_ Net-_U19-Pad1_ d_nand +U23 Net-_U23-Pad1_ Net-_U10-Pad2_ Net-_U18-Pad1_ d_and +U19 Net-_U19-Pad1_ Net-_U19-Pad2_ dac_bridge_1 +U18 Net-_U18-Pad1_ Net-_U18-Pad2_ dac_bridge_1 +U24 Net-_U20-Pad1_ Net-_U21-Pad1_ d_inverter +U21 Net-_U21-Pad1_ Net-_U20-Pad2_ Net-_U16-Pad1_ d_and +U16 Net-_U16-Pad1_ Net-_U16-Pad2_ dac_bridge_1 +U20 Net-_U20-Pad1_ Net-_U20-Pad2_ Net-_U17-Pad1_ d_nand +U17 Net-_U17-Pad1_ Net-_U17-Pad2_ dac_bridge_1 +U5 EnB Net-_U10-Pad2_ adc_bridge_1 +U7 Net-_U10-Pad1_ Net-_U11-Pad1_ d_inverter +U11 Net-_U11-Pad1_ Net-_U10-Pad2_ Net-_U11-Pad3_ d_and +U3 INPUT3 Net-_U10-Pad1_ adc_bridge_1 +U2 INPUT1 Net-_U2-Pad2_ adc_bridge_1 +U15 Net-_U11-Pad3_ Net-_U15-Pad2_ dac_bridge_1 +Q4 out3 Net-_U15-Pad2_ GND eSim_NPN +Q8 out4 Net-_U18-Pad2_ GND eSim_NPN +.end diff --git a/library/SubcircuitLibrary/L298N/L298N.cir.out b/library/SubcircuitLibrary/L298N/L298N.cir.out new file mode 100644 index 000000000..82922999c --- /dev/null +++ b/library/SubcircuitLibrary/L298N/L298N.cir.out @@ -0,0 +1,126 @@ +.title kicad schematic + +.include PNP.lib +.include NPN.lib +* u1 gnd out1 out2 vdd input1 ena input2 gnd unconnected-_u1-pad9_ input3 enb input4 out3 out4 gnd port +q2 out1 net-_u13-pad2_ gnd Q2N2222 +q5 out2 net-_u17-pad2_ vdd Q2N2907A +q1 out1 net-_u12-pad2_ vdd Q2N2907A +q6 out2 net-_u16-pad2_ gnd Q2N2222 +* u14 net-_u10-pad3_ net-_u14-pad2_ dac_bridge_1 +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nand +q7 out4 net-_u19-pad2_ vdd Q2N2907A +q3 out3 net-_u14-pad2_ vdd Q2N2907A +* u27 input4 net-_u22-pad1_ adc_bridge_1 +* u25 net-_u22-pad1_ net-_u23-pad1_ d_inverter +* u26 input2 net-_u20-pad1_ adc_bridge_1 +* u12 net-_u12-pad1_ net-_u12-pad2_ dac_bridge_1 +* u13 net-_u13-pad1_ net-_u13-pad2_ dac_bridge_1 +* u6 net-_u2-pad2_ net-_u6-pad2_ d_inverter +* u8 net-_u2-pad2_ net-_u20-pad2_ net-_u12-pad1_ d_nand +* u9 net-_u6-pad2_ net-_u20-pad2_ net-_u13-pad1_ d_and +* u4 ena net-_u20-pad2_ adc_bridge_1 +* u22 net-_u22-pad1_ net-_u10-pad2_ net-_u19-pad1_ d_nand +* u23 net-_u23-pad1_ net-_u10-pad2_ net-_u18-pad1_ d_and +* u19 net-_u19-pad1_ net-_u19-pad2_ dac_bridge_1 +* u18 net-_u18-pad1_ net-_u18-pad2_ dac_bridge_1 +* u24 net-_u20-pad1_ net-_u21-pad1_ d_inverter +* u21 net-_u21-pad1_ net-_u20-pad2_ net-_u16-pad1_ d_and +* u16 net-_u16-pad1_ net-_u16-pad2_ dac_bridge_1 +* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u17-pad1_ d_nand +* u17 net-_u17-pad1_ net-_u17-pad2_ dac_bridge_1 +* u5 enb net-_u10-pad2_ adc_bridge_1 +* u7 net-_u10-pad1_ net-_u11-pad1_ d_inverter +* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_and +* u3 input3 net-_u10-pad1_ adc_bridge_1 +* u2 input1 net-_u2-pad2_ adc_bridge_1 +* u15 net-_u11-pad3_ net-_u15-pad2_ dac_bridge_1 +q4 out3 net-_u15-pad2_ gnd Q2N2222 +q8 out4 net-_u18-pad2_ gnd Q2N2222 +a1 [net-_u10-pad3_ ] [net-_u14-pad2_ ] u14 +a2 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a3 [input4 ] [net-_u22-pad1_ ] u27 +a4 net-_u22-pad1_ net-_u23-pad1_ u25 +a5 [input2 ] [net-_u20-pad1_ ] u26 +a6 [net-_u12-pad1_ ] [net-_u12-pad2_ ] u12 +a7 [net-_u13-pad1_ ] [net-_u13-pad2_ ] u13 +a8 net-_u2-pad2_ net-_u6-pad2_ u6 +a9 [net-_u2-pad2_ net-_u20-pad2_ ] net-_u12-pad1_ u8 +a10 [net-_u6-pad2_ net-_u20-pad2_ ] net-_u13-pad1_ u9 +a11 [ena ] [net-_u20-pad2_ ] u4 +a12 [net-_u22-pad1_ net-_u10-pad2_ ] net-_u19-pad1_ u22 +a13 [net-_u23-pad1_ net-_u10-pad2_ ] net-_u18-pad1_ u23 +a14 [net-_u19-pad1_ ] [net-_u19-pad2_ ] u19 +a15 [net-_u18-pad1_ ] [net-_u18-pad2_ ] u18 +a16 net-_u20-pad1_ net-_u21-pad1_ u24 +a17 [net-_u21-pad1_ net-_u20-pad2_ ] net-_u16-pad1_ u21 +a18 [net-_u16-pad1_ ] [net-_u16-pad2_ ] u16 +a19 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u17-pad1_ u20 +a20 [net-_u17-pad1_ ] [net-_u17-pad2_ ] u17 +a21 [enb ] [net-_u10-pad2_ ] u5 +a22 net-_u10-pad1_ net-_u11-pad1_ u7 +a23 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11 +a24 [input3 ] [net-_u10-pad1_ ] u3 +a25 [input1 ] [net-_u2-pad2_ ] u2 +a26 [net-_u11-pad3_ ] [net-_u15-pad2_ ] u15 +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u14 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u10 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u27 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u26 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u12 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u13 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u4 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u22 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u19 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u18 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u16 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u20 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u17 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u5 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u15 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print 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(path "/b0ef0cd0-e232-488c-ae19-1656c78e1b09" + (reference "U2") (unit 1) (value "adc_bridge_1") (footprint "") + ) + (path "/c0708dfd-77c7-46ba-969c-c44998c5ad20" + (reference "U3") (unit 1) (value "adc_bridge_1") (footprint "") + ) + (path "/084f4fc6-efe7-4677-ba9c-87755261eb0c" + (reference "U4") (unit 1) (value "adc_bridge_1") (footprint "") + ) + (path "/36196a2c-2945-47e8-bd7e-3f7ba71582db" + (reference "U5") (unit 1) (value "adc_bridge_1") (footprint "") + ) + (path "/2d892775-5e7a-41e9-9d05-603cef04f891" + (reference "U6") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/7e00e8da-0644-420c-b2f5-db2feb57d3a4" + (reference "U7") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/fc47c641-1d3c-4770-a2a7-cabbaa164d83" + (reference "U8") (unit 1) (value "d_nand") (footprint "") + ) + (path "/be64de43-f94a-4aef-bcb1-895f731f5e0a" + (reference "U9") (unit 1) (value "d_and") (footprint "") + ) + (path "/74733021-0f03-49c1-a5b5-5724140e116d" + (reference "U10") (unit 1) (value "d_nand") (footprint "") + ) + (path "/16673c8c-e1d8-449a-9d52-0b0890439993" + (reference "U11") (unit 1) (value "d_and") (footprint "") + ) + (path "/3b3cfd07-ffdd-4218-b7fb-1c6e3a2360d1" + (reference "U12") (unit 1) (value "dac_bridge_1") (footprint "") + ) + (path "/d5295ded-9535-4c8f-8d4b-23242f55ce59" + (reference "U13") (unit 1) (value "dac_bridge_1") (footprint "") + ) + (path "/ba553bee-c2e3-4d82-b986-37a717a4702e" + (reference "U14") (unit 1) (value "dac_bridge_1") (footprint "") + ) + (path "/94f0f632-f9f9-423b-b960-7714ec2e34ce" + (reference "U15") (unit 1) (value "dac_bridge_1") (footprint "") + ) + (path "/585d907f-6231-444c-86e3-ba0f74b7c914" + (reference "U16") (unit 1) (value "dac_bridge_1") (footprint "") + ) + (path "/561fa476-3d84-40c9-82ce-23826e51b398" + (reference "U17") (unit 1) (value "dac_bridge_1") (footprint "") + ) + (path "/22ad295a-95bb-4dca-8095-dc4331651b2d" + (reference "U18") (unit 1) (value "dac_bridge_1") (footprint "") + ) + (path "/4763337e-1ad3-4d53-82ed-f1a2c1ddca41" + (reference "U19") (unit 1) (value "dac_bridge_1") (footprint "") + ) + (path "/ea6f1204-8c0c-43cc-b9cb-4a49d509ce35" + (reference "U20") (unit 1) (value "d_nand") (footprint "") + ) + (path "/3d9fe850-2d6a-4386-81ec-6fc26b446801" + (reference "U21") (unit 1) (value "d_and") (footprint "") + ) + (path "/3ae935ae-797a-45c8-82b2-a7b6af546853" + (reference "U22") (unit 1) (value "d_nand") (footprint "") + ) + (path "/4253257c-834f-40a3-922a-f16a6533aa82" + (reference "U23") (unit 1) (value "d_and") (footprint "") + ) + (path "/738584b9-375f-4523-8dae-ddd2fc34513d" + (reference "U24") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/c5576fb3-8514-4c8b-acab-a5f1b7d2cdc2" + (reference "U25") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/dd9c653d-b8e6-4105-b808-222fe1b64544" + (reference "U26") (unit 1) (value "adc_bridge_1") (footprint "") + ) + (path "/e4bc7b44-ebfc-4658-9632-8bc9873df8c0" + (reference "U27") (unit 1) (value "adc_bridge_1") (footprint "") + ) + ) +) diff --git a/library/SubcircuitLibrary/L298N/L298N.sub b/library/SubcircuitLibrary/L298N/L298N.sub new file mode 100644 index 000000000..46d49d75e --- /dev/null +++ b/library/SubcircuitLibrary/L298N/L298N.sub @@ -0,0 +1,120 @@ +* Subcircuit L298N +.subckt L298N gnd out1 out2 vdd input1 ena input2 gnd unconnected-_u1-pad9_ input3 enb input4 out3 out4 gnd +.title kicad schematic +.include PNP.lib +.include NPN.lib +q2 out1 net-_u13-pad2_ gnd Q2N2222 +q5 out2 net-_u17-pad2_ vdd Q2N2907A +q1 out1 net-_u12-pad2_ vdd Q2N2907A +q6 out2 net-_u16-pad2_ gnd Q2N2222 +* u14 net-_u10-pad3_ net-_u14-pad2_ dac_bridge_1 +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nand +q7 out4 net-_u19-pad2_ vdd Q2N2907A +q3 out3 net-_u14-pad2_ vdd Q2N2907A +* u27 input4 net-_u22-pad1_ adc_bridge_1 +* u25 net-_u22-pad1_ net-_u23-pad1_ d_inverter +* u26 input2 net-_u20-pad1_ adc_bridge_1 +* u12 net-_u12-pad1_ net-_u12-pad2_ dac_bridge_1 +* u13 net-_u13-pad1_ net-_u13-pad2_ dac_bridge_1 +* u6 net-_u2-pad2_ net-_u6-pad2_ d_inverter +* u8 net-_u2-pad2_ net-_u20-pad2_ net-_u12-pad1_ d_nand +* u9 net-_u6-pad2_ net-_u20-pad2_ net-_u13-pad1_ d_and +* u4 ena net-_u20-pad2_ adc_bridge_1 +* u22 net-_u22-pad1_ net-_u10-pad2_ net-_u19-pad1_ d_nand +* u23 net-_u23-pad1_ net-_u10-pad2_ net-_u18-pad1_ d_and +* u19 net-_u19-pad1_ net-_u19-pad2_ dac_bridge_1 +* u18 net-_u18-pad1_ net-_u18-pad2_ dac_bridge_1 +* u24 net-_u20-pad1_ net-_u21-pad1_ d_inverter +* u21 net-_u21-pad1_ net-_u20-pad2_ net-_u16-pad1_ d_and +* u16 net-_u16-pad1_ net-_u16-pad2_ dac_bridge_1 +* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u17-pad1_ d_nand +* u17 net-_u17-pad1_ net-_u17-pad2_ dac_bridge_1 +* u5 enb net-_u10-pad2_ adc_bridge_1 +* u7 net-_u10-pad1_ net-_u11-pad1_ d_inverter +* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_and +* u3 input3 net-_u10-pad1_ adc_bridge_1 +* u2 input1 net-_u2-pad2_ adc_bridge_1 +* u15 net-_u11-pad3_ net-_u15-pad2_ dac_bridge_1 +q4 out3 net-_u15-pad2_ gnd Q2N2222 +q8 out4 net-_u18-pad2_ gnd Q2N2222 +a1 [net-_u10-pad3_ ] [net-_u14-pad2_ ] u14 +a2 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a3 [input4 ] [net-_u22-pad1_ ] u27 +a4 net-_u22-pad1_ net-_u23-pad1_ u25 +a5 [input2 ] [net-_u20-pad1_ ] u26 +a6 [net-_u12-pad1_ ] [net-_u12-pad2_ ] u12 +a7 [net-_u13-pad1_ ] [net-_u13-pad2_ ] u13 +a8 net-_u2-pad2_ net-_u6-pad2_ u6 +a9 [net-_u2-pad2_ net-_u20-pad2_ ] net-_u12-pad1_ u8 +a10 [net-_u6-pad2_ net-_u20-pad2_ ] net-_u13-pad1_ u9 +a11 [ena ] [net-_u20-pad2_ ] u4 +a12 [net-_u22-pad1_ net-_u10-pad2_ ] net-_u19-pad1_ u22 +a13 [net-_u23-pad1_ net-_u10-pad2_ ] net-_u18-pad1_ u23 +a14 [net-_u19-pad1_ ] [net-_u19-pad2_ ] u19 +a15 [net-_u18-pad1_ ] [net-_u18-pad2_ ] u18 +a16 net-_u20-pad1_ net-_u21-pad1_ u24 +a17 [net-_u21-pad1_ net-_u20-pad2_ ] net-_u16-pad1_ u21 +a18 [net-_u16-pad1_ ] [net-_u16-pad2_ ] u16 +a19 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u17-pad1_ u20 +a20 [net-_u17-pad1_ ] [net-_u17-pad2_ ] u17 +a21 [enb ] [net-_u10-pad2_ ] u5 +a22 net-_u10-pad1_ net-_u11-pad1_ u7 +a23 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11 +a24 [input3 ] [net-_u10-pad1_ ] u3 +a25 [input1 ] [net-_u2-pad2_ ] u2 +a26 [net-_u11-pad3_ ] [net-_u15-pad2_ ] u15 +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u14 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u10 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u27 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u26 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u12 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u13 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u4 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u22 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u19 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u18 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u16 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u20 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u17 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u5 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u15 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Control Statements + +.ends L298N \ No newline at end of file diff --git a/library/SubcircuitLibrary/L298N/L298N_Previous_Values.xml b/library/SubcircuitLibrary/L298N/L298N_Previous_Values.xml new file mode 100644 index 000000000..e12298eed --- /dev/null +++ b/library/SubcircuitLibrary/L298N/L298N_Previous_Values.xml @@ -0,0 +1 @@ +dac_bridgedac_bridgedac_bridgedac_bridged_nandd_inverterd_anddac_bridged_inverterd_nandd_andd_nanddac_bridgedac_bridged_andd_nandd_inverteradc_bridgeadc_bridgeadc_bridgeadc_bridgedac_bridged_andadc_bridgeadc_bridged_inverterC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/L298N/NMOS-180nm.lib b/library/SubcircuitLibrary/L298N/NMOS-180nm.lib new file mode 100644 index 000000000..51e9b1196 --- /dev/null +++ b/library/SubcircuitLibrary/L298N/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/L298N/NPN.lib b/library/SubcircuitLibrary/L298N/NPN.lib new file mode 100644 index 000000000..be5f3073a --- /dev/null +++ b/library/SubcircuitLibrary/L298N/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/L298N/PMOS-180nm.lib b/library/SubcircuitLibrary/L298N/PMOS-180nm.lib new file mode 100644 index 000000000..032b5b95e --- /dev/null +++ b/library/SubcircuitLibrary/L298N/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/L298N/PNP.lib b/library/SubcircuitLibrary/L298N/PNP.lib new file mode 100644 index 000000000..7edda0eab --- /dev/null +++ b/library/SubcircuitLibrary/L298N/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/L298N/_autosave-L298N.sch b/library/SubcircuitLibrary/L298N/_autosave-L298N.sch new file mode 100644 index 000000000..1b98048ba --- /dev/null +++ b/library/SubcircuitLibrary/L298N/_autosave-L298N.sch @@ -0,0 +1,817 @@ +EESchema Schematic File Version 5 +EELAYER 36 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +Comment5 "" +Comment6 "" +Comment7 "" +Comment8 "" +Comment9 "" +$EndDescr +Connection ~ -11700 3550 +Connection ~ -11650 6450 +Connection ~ -11200 4650 +Connection ~ -11150 1900 +Connection ~ -10450 3150 +Connection ~ -10400 5900 +Connection ~ -9800 1950 +Connection ~ -9800 2350 +Connection ~ -9750 4700 +Connection ~ -9750 5100 +Connection ~ -7100 1650 +Connection ~ -7100 2800 +Connection ~ -7100 3650 +Connection ~ -7100 3750 +Connection ~ -7050 5550 +Connection ~ -7050 6400 +Connection ~ -7050 6500 +Connection ~ -5950 2800 +Connection ~ -5900 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-1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 6 1 00000000 +P -11400 1700 +F 0 "U1" H -11375 1900 30 0000 C CNN +F 1 "PORT" H -11375 1800 30 0000 C CNN +F 2 "" H -11400 1700 60 0000 C CNN +F 3 "" H -11400 1700 60 0000 C CNN + 6 -11400 1700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 4 1 00000000 +P -7350 1650 +F 0 "U1" H -7325 1850 30 0000 C CNN +F 1 "PORT" H -7325 1750 30 0000 C CNN +F 2 "" H -7350 1650 60 0000 C CNN +F 3 "" H -7350 1650 60 0000 C CNN + 4 -7350 1650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 2 1 00000000 +P -7350 2800 +F 0 "U1" H -7325 3000 30 0000 C CNN +F 1 "PORT" H -7325 2900 30 0000 C CNN +F 2 "" H -7350 2800 60 0000 C CNN +F 3 "" H -7350 2800 60 0000 C CNN + 2 -7350 2800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 1 1 00000000 +P -7350 3650 +F 0 "U1" H -7325 3850 30 0000 C CNN +F 1 "PORT" H -7325 3750 30 0000 C CNN +F 2 "" H -7350 3650 60 0000 C CNN +F 3 "" H -7350 3650 60 0000 C CNN + 1 -7350 3650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 13 1 00000000 +P -7300 5550 +F 0 "U1" H -7275 5750 30 0000 C CNN +F 1 "PORT" H -7275 5650 30 0000 C CNN +F 2 "" H -7300 5550 60 0000 C CNN +F 3 "" H -7300 5550 60 0000 C CNN + 13 -7300 5550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 8 1 00000000 +P -7300 6400 +F 0 "U1" H -7275 6600 30 0000 C CNN +F 1 "PORT" H -7275 6500 30 0000 C CNN +F 2 "" H -7300 6400 60 0000 C CNN +F 3 "" H -7300 6400 60 0000 C CNN + 8 -7300 6400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 3 1 00000000 +P -6200 2800 +F 0 "U1" H -6175 3000 30 0000 C CNN +F 1 "PORT" H -6175 2900 30 0000 C CNN +F 2 "" H -6200 2800 60 0000 C CNN +F 3 "" H -6200 2800 60 0000 C CNN + 3 -6200 2800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 14 1 00000000 +P -6150 5550 +F 0 "U1" H -6125 5750 30 0000 C CNN +F 1 "PORT" H -6125 5650 30 0000 C CNN +F 2 "" H -6150 5550 60 0000 C CNN +F 3 "" H -6150 5550 60 0000 C CNN + 14 -6150 5550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 15 1 00000000 +P -6150 6400 +F 0 "U1" H -6125 6600 30 0000 C CNN +F 1 "PORT" H -6125 6500 30 0000 C CNN +F 2 "" H -6150 6400 60 0000 C CNN +F 3 "" H -6150 6400 60 0000 C CNN + 15 -6150 6400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 7 1 00000000 +P -1750 4450 +F 0 "U1" H -1725 4650 30 0000 C CNN +F 1 "PORT" H -1725 4550 30 0000 C CNN +F 2 "" H -1750 4450 60 0000 C CNN +F 3 "" H -1750 4450 60 0000 C CNN + 7 -1750 4450 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U1 +U 12 1 00000000 +P -1700 7100 +F 0 "U1" H -1675 7300 30 0000 C CNN +F 1 "PORT" H -1675 7200 30 0000 C CNN +F 2 "" H -1700 7100 60 0000 C CNN +F 3 "" H -1700 7100 60 0000 C CNN + 12 -1700 7100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_inverter U6 +U 1 1 00000000 +P -10150 3150 +F 0 "U6" H -10150 2900 60 0000 C CNN +F 1 "d_inverter" H -10150 3050 60 0000 C CNN +F 2 "" H -10100 3100 60 0000 C CNN +F 3 "" H -10100 3100 60 0000 C CNN + 1 -10150 3150 + 1 0 0 1 +$EndComp +$Comp +L eSim_Digital:d_inverter U7 +U 1 1 00000000 +P -10100 5900 +F 0 "U7" H -10100 5650 60 0000 C CNN +F 1 "d_inverter" H -10100 5800 60 0000 C CNN +F 2 "" H -10050 5850 60 0000 C CNN +F 3 "" H -10050 5850 60 0000 C CNN + 1 -10100 5900 + 1 0 0 1 +$EndComp +$Comp +L eSim_Digital:d_inverter U24 +U 1 1 00000000 +P -2900 3100 +F 0 "U24" H -2900 2850 60 0000 C CNN +F 1 "d_inverter" H -2900 3000 60 0000 C CNN +F 2 "" H -2850 3050 60 0000 C CNN +F 3 "" H -2850 3050 60 0000 C CNN + 1 -2900 3100 + -1 0 0 1 +$EndComp +$Comp +L eSim_Digital:d_inverter U25 +U 1 1 00000000 +P -2850 5850 +F 0 "U25" H -2850 5600 60 0000 C CNN +F 1 "d_inverter" H -2850 5750 60 0000 C CNN +F 2 "" H -2800 5800 60 0000 C CNN +F 3 "" H -2800 5800 60 0000 C CNN + 1 -2850 5850 + -1 0 0 1 +$EndComp +$Comp +L eSim_Devices:eSim_PNP Q1 +U 1 1 00000000 +P -7200 2300 +F 0 "Q1" H -7000 2250 50 0000 L CNN +F 1 "eSim_PNP" H -7000 2350 50 0000 L CNN +F 2 "" H -7000 2400 29 0000 C CNN +F 3 "" H -7200 2300 60 0000 C CNN + 1 -7200 2300 + 1 0 0 1 +$EndComp +$Comp +L eSim_Devices:eSim_NPN Q2 +U 1 1 00000000 +P -7200 3200 +F 0 "Q2" H -7000 3250 50 0000 L CNN +F 1 "eSim_NPN" H -7000 3150 50 0000 L CNN +F 2 "" H -7000 3300 29 0000 C CNN +F 3 "" H -7200 3200 60 0000 C CNN + 1 -7200 3200 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Devices:eSim_PNP Q3 +U 1 1 00000000 +P -7150 5050 +F 0 "Q3" H -6950 5000 50 0000 L CNN +F 1 "eSim_PNP" H -6950 5100 50 0000 L CNN +F 2 "" H -6950 5150 29 0000 C CNN +F 3 "" H -7150 5050 60 0000 C CNN + 1 -7150 5050 + 1 0 0 1 +$EndComp +$Comp +L eSim_Devices:eSim_NPN Q4 +U 1 1 00000000 +P -7150 5950 +F 0 "Q4" H -6950 6000 50 0000 L CNN +F 1 "eSim_NPN" H -6950 5900 50 0000 L CNN +F 2 "" H -6950 6050 29 0000 C CNN +F 3 "" H -7150 5950 60 0000 C CNN + 1 -7150 5950 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Devices:eSim_PNP Q5 +U 1 1 00000000 +P -5850 2250 +F 0 "Q5" H -5650 2200 50 0000 L CNN +F 1 "eSim_PNP" H -5650 2300 50 0000 L CNN +F 2 "" H -5650 2350 29 0000 C CNN +F 3 "" H -5850 2250 60 0000 C CNN + 1 -5850 2250 + -1 0 0 1 +$EndComp +$Comp +L eSim_Devices:eSim_NPN Q6 +U 1 1 00000000 +P -5850 3150 +F 0 "Q6" H -5650 3200 50 0000 L CNN +F 1 "eSim_NPN" H -5650 3100 50 0000 L CNN +F 2 "" H -5650 3250 29 0000 C CNN +F 3 "" H -5850 3150 60 0000 C CNN + 1 -5850 3150 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Devices:eSim_PNP Q7 +U 1 1 00000000 +P -5800 5000 +F 0 "Q7" H -5600 4950 50 0000 L CNN +F 1 "eSim_PNP" H -5600 5050 50 0000 L CNN +F 2 "" H -5600 5100 29 0000 C CNN +F 3 "" H -5800 5000 60 0000 C CNN + 1 -5800 5000 + -1 0 0 1 +$EndComp +$Comp +L eSim_Devices:eSim_NPN Q8 +U 1 1 00000000 +P -5800 5900 +F 0 "Q8" H -5600 5950 50 0000 L CNN +F 1 "eSim_NPN" H -5600 5850 50 0000 L CNN +F 2 "" H -5600 6000 29 0000 C CNN +F 3 "" H -5800 5900 60 0000 C CNN + 1 -5800 5900 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_nand U8 +U 1 1 00000000 +P -9200 2350 +F 0 "U8" H -9200 2700 60 0000 C CNN +F 1 "d_nand" H -9200 2550 60 0000 C CNN +F 2 "" H -9200 2350 60 0000 C CNN +F 3 "" H -9200 2350 60 0000 C CNN + 1 -9200 2350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_and U9 +U 1 1 00000000 +P -9200 3250 +F 0 "U9" H -9200 3600 60 0000 C CNN +F 1 "d_and" H -9200 3450 60 0000 C CNN +F 2 "" H -9200 3250 60 0000 C CNN +F 3 "" H -9200 3250 60 0000 C CNN + 1 -9200 3250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_nand U10 +U 1 1 00000000 +P -9150 5100 +F 0 "U10" H -9150 5450 60 0000 C CNN +F 1 "d_nand" H -9150 5300 60 0000 C CNN +F 2 "" H -9150 5100 60 0000 C CNN +F 3 "" H -9150 5100 60 0000 C CNN + 1 -9150 5100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_and U11 +U 1 1 00000000 +P -9150 6000 +F 0 "U11" H -9150 6350 60 0000 C CNN +F 1 "d_and" H -9150 6200 60 0000 C CNN +F 2 "" H -9150 6000 60 0000 C CNN +F 3 "" H -9150 6000 60 0000 C CNN + 1 -9150 6000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_nand U20 +U 1 1 00000000 +P -3850 2300 +F 0 "U20" H -3850 2650 60 0000 C CNN +F 1 "d_nand" H -3850 2500 60 0000 C CNN +F 2 "" H -3850 2300 60 0000 C CNN +F 3 "" H -3850 2300 60 0000 C CNN + 1 -3850 2300 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_and U21 +U 1 1 00000000 +P -3850 3200 +F 0 "U21" H -3850 3550 60 0000 C CNN +F 1 "d_and" H -3850 3400 60 0000 C CNN +F 2 "" H -3850 3200 60 0000 C CNN +F 3 "" H -3850 3200 60 0000 C CNN + 1 -3850 3200 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_nand U22 +U 1 1 00000000 +P -3800 5050 +F 0 "U22" H -3800 5400 60 0000 C CNN +F 1 "d_nand" H -3800 5250 60 0000 C CNN +F 2 "" H -3800 5050 60 0000 C CNN +F 3 "" H -3800 5050 60 0000 C CNN + 1 -3800 5050 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_and U23 +U 1 1 00000000 +P -3800 5950 +F 0 "U23" H -3800 6300 60 0000 C CNN +F 1 "d_and" H -3800 6150 60 0000 C CNN +F 2 "" H -3800 5950 60 0000 C CNN +F 3 "" H -3800 5950 60 0000 C CNN + 1 -3800 5950 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Hybrid:adc_bridge_1 U2 +U 1 1 00000000 +P -11000 3600 +F 0 "U2" V -10975 3500 60 0000 R CNN +F 1 "adc_bridge_1" V -11125 3500 60 0000 R CNN +F 2 "" H -11000 3600 60 0000 C CNN +F 3 "" H -11000 3600 60 0000 C CNN + 1 -11000 3600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Hybrid:adc_bridge_1 U3 +U 1 1 00000000 +P -10950 6350 +F 0 "U3" V -10925 6250 60 0000 R CNN +F 1 "adc_bridge_1" V -11075 6250 60 0000 R CNN +F 2 "" H -10950 6350 60 0000 C CNN +F 3 "" H -10950 6350 60 0000 C CNN + 1 -10950 6350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Hybrid:adc_bridge_1 U4 +U 1 1 00000000 +P -10400 1950 +F 0 "U4" H -10425 2350 60 0000 C CNN +F 1 "adc_bridge_1" H -10425 2200 60 0000 C CNN +F 2 "" H -10400 1950 60 0000 C CNN +F 3 "" H -10400 1950 60 0000 C CNN + 1 -10400 1950 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Hybrid:adc_bridge_1 U5 +U 1 1 00000000 +P -10350 4700 +F 0 "U5" H -10375 5100 60 0000 C CNN +F 1 "adc_bridge_1" H -10375 4950 60 0000 C CNN +F 2 "" H -10350 4700 60 0000 C CNN +F 3 "" H -10350 4700 60 0000 C CNN + 1 -10350 4700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Hybrid:dac_bridge_1 U12 +U 1 1 00000000 +P -7950 2350 +F 0 "U12" H -7975 2750 60 0000 C CNN +F 1 "dac_bridge_1" H -7975 2600 60 0000 C CNN +F 2 "" H -7950 2350 60 0000 C CNN +F 3 "" H -7950 2350 60 0000 C CNN + 1 -7950 2350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Hybrid:dac_bridge_1 U13 +U 1 1 00000000 +P -7950 3250 +F 0 "U13" H -7975 3650 60 0000 C CNN +F 1 "dac_bridge_1" H -7975 3500 60 0000 C CNN +F 2 "" H -7950 3250 60 0000 C CNN +F 3 "" H -7950 3250 60 0000 C CNN + 1 -7950 3250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Hybrid:dac_bridge_1 U14 +U 1 1 00000000 +P -7900 5100 +F 0 "U14" H -7925 5500 60 0000 C CNN +F 1 "dac_bridge_1" H -7925 5350 60 0000 C CNN +F 2 "" H -7900 5100 60 0000 C CNN +F 3 "" H -7900 5100 60 0000 C CNN + 1 -7900 5100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Hybrid:dac_bridge_1 U15 +U 1 1 00000000 +P -7900 6000 +F 0 "U15" H -7925 6400 60 0000 C CNN +F 1 "dac_bridge_1" H -7925 6250 60 0000 C CNN +F 2 "" H -7900 6000 60 0000 C CNN +F 3 "" H -7900 6000 60 0000 C CNN + 1 -7900 6000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Hybrid:dac_bridge_1 U16 +U 1 1 00000000 +P -5100 3200 +F 0 "U16" H -5125 3600 60 0000 C CNN +F 1 "dac_bridge_1" H -5125 3450 60 0000 C CNN +F 2 "" H -5100 3200 60 0000 C CNN +F 3 "" H -5100 3200 60 0000 C CNN + 1 -5100 3200 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Hybrid:dac_bridge_1 U17 +U 1 1 00000000 +P -5050 2300 +F 0 "U17" H -5075 2700 60 0000 C CNN +F 1 "dac_bridge_1" H -5075 2550 60 0000 C CNN +F 2 "" H -5050 2300 60 0000 C CNN +F 3 "" H -5050 2300 60 0000 C CNN + 1 -5050 2300 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Hybrid:dac_bridge_1 U18 +U 1 1 00000000 +P -5050 5950 +F 0 "U18" H -5075 6350 60 0000 C CNN +F 1 "dac_bridge_1" H -5075 6200 60 0000 C CNN +F 2 "" H -5050 5950 60 0000 C CNN +F 3 "" H -5050 5950 60 0000 C CNN + 1 -5050 5950 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Hybrid:dac_bridge_1 U19 +U 1 1 00000000 +P -5000 5050 +F 0 "U19" H -5025 5450 60 0000 C CNN +F 1 "dac_bridge_1" H -5025 5300 60 0000 C CNN +F 2 "" H -5000 5050 60 0000 C CNN +F 3 "" H -5000 5050 60 0000 C CNN + 1 -5000 5050 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Hybrid:adc_bridge_1 U26 +U 1 1 00000000 +P -2050 3600 +F 0 "U26" H -2075 3350 60 0000 C CNN +F 1 "adc_bridge_1" H -2075 3500 60 0000 C CNN +F 2 "" H -2050 3600 60 0000 C CNN +F 3 "" H -2050 3600 60 0000 C CNN + 1 -2050 3600 + -1 0 0 1 +$EndComp +$Comp +L eSim_Hybrid:adc_bridge_1 U27 +U 1 1 00000000 +P -2000 6350 +F 0 "U27" H -2025 6100 60 0000 C CNN +F 1 "adc_bridge_1" H -2025 6250 60 0000 C CNN +F 2 "" H -2000 6350 60 0000 C CNN +F 3 "" H -2000 6350 60 0000 C CNN + 1 -2000 6350 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/L298N/analysis b/library/SubcircuitLibrary/L298N/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/L298N/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/LM3914/D.lib b/library/SubcircuitLibrary/LM3914/D.lib new file mode 100644 index 000000000..f53bf3e03 --- /dev/null +++ b/library/SubcircuitLibrary/LM3914/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/LM3914/IC_LM397MFX-cache.lib b/library/SubcircuitLibrary/LM3914/IC_LM397MFX-cache.lib new file mode 100644 index 000000000..6b1c27a73 --- /dev/null +++ b/library/SubcircuitLibrary/LM3914/IC_LM397MFX-cache.lib @@ -0,0 +1,159 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_GND +# +DEF eSim_GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "eSim_GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# eSim_NJF +# +DEF eSim_NJF J 0 0 Y N 1 F N +F0 "J" -100 50 50 H V R CNN +F1 "eSim_NJF" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS jfet_n +DRAW +C 50 0 111 0 1 10 N +P 3 0 1 10 10 75 10 -75 10 -75 N +P 3 0 1 0 100 -100 100 -50 10 -50 N +P 3 0 1 0 100 100 100 55 10 55 N +P 4 0 1 0 0 0 -40 15 -40 -15 0 0 F +X D 1 100 200 100 D 50 50 1 1 P +X G 2 -200 0 210 R 50 50 1 1 P +X S 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/LM3914/IC_LM397MFX.cir b/library/SubcircuitLibrary/LM3914/IC_LM397MFX.cir new file mode 100644 index 000000000..9ad5f5c50 --- /dev/null +++ b/library/SubcircuitLibrary/LM3914/IC_LM397MFX.cir @@ -0,0 +1,36 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\IC_LM397MFX\IC_LM397MFX.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/20/23 21:50:19 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +J1 Net-_J1-Pad1_ GND Net-_J1-Pad3_ jfet_n +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q4 Net-_J1-Pad3_ Net-_Q1-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q5 Net-_Q2-Pad3_ Net-_Q1-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q8 Net-_D4-Pad1_ Net-_Q1-Pad1_ Net-_Q7-Pad3_ eSim_PNP +Q7 Net-_D2-Pad1_ Net-_Q1-Pad1_ Net-_Q7-Pad3_ eSim_PNP +Q10 Net-_Q10-Pad1_ Net-_Q1-Pad1_ Net-_J1-Pad1_ eSim_PNP +R2 Net-_Q1-Pad1_ Net-_Q1-Pad2_ 2k +R3 Net-_J1-Pad1_ Net-_Q7-Pad3_ 2.1k +Q2 Net-_Q1-Pad1_ Net-_J1-Pad3_ Net-_Q2-Pad3_ eSim_NPN +Q3 Net-_J1-Pad3_ Net-_Q2-Pad3_ GND eSim_NPN +D2 Net-_D2-Pad1_ Net-_D1-Pad2_ eSim_Diode +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +Q6 GND Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_PNP +Q9 Net-_D3-Pad1_ Net-_D1-Pad2_ Net-_Q10-Pad1_ eSim_PNP +Q12 Net-_Q11-Pad1_ Net-_D4-Pad2_ Net-_Q10-Pad1_ eSim_PNP +Q13 GND Net-_D5-Pad1_ Net-_D4-Pad2_ eSim_PNP +D4 Net-_D4-Pad1_ Net-_D4-Pad2_ eSim_Diode +D5 Net-_D5-Pad1_ Net-_D4-Pad2_ eSim_Diode +R1 Net-_Q2-Pad3_ GND 4.8k +Q11 Net-_Q11-Pad1_ Net-_D3-Pad1_ GND eSim_NPN +D3 Net-_D3-Pad1_ GND eSim_Diode +Q14 Net-_Q14-Pad1_ Net-_Q1-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q15 Net-_Q14-Pad1_ Net-_Q11-Pad1_ GND eSim_NPN +Q16 Net-_Q16-Pad1_ Net-_Q14-Pad1_ GND eSim_NPN +U1 Net-_J1-Pad1_ Net-_D1-Pad1_ Net-_D5-Pad1_ Net-_Q16-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/LM3914/IC_LM397MFX.cir.out b/library/SubcircuitLibrary/LM3914/IC_LM397MFX.cir.out new file mode 100644 index 000000000..ad964b909 --- /dev/null +++ b/library/SubcircuitLibrary/LM3914/IC_LM397MFX.cir.out @@ -0,0 +1,41 @@ +* c:\fossee\esim\library\subcircuitlibrary\ic_lm397mfx\ic_lm397mfx.cir + +.include NPN.lib +.include D.lib +.include PNP.lib +.include NJF.lib +j1 net-_j1-pad1_ gnd net-_j1-pad3_ J2N3819 +q1 net-_q1-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q4 net-_j1-pad3_ net-_q1-pad1_ net-_j1-pad1_ Q2N2907A +q5 net-_q2-pad3_ net-_q1-pad1_ net-_j1-pad1_ Q2N2907A +q8 net-_d4-pad1_ net-_q1-pad1_ net-_q7-pad3_ Q2N2907A +q7 net-_d2-pad1_ net-_q1-pad1_ net-_q7-pad3_ Q2N2907A +q10 net-_q10-pad1_ net-_q1-pad1_ net-_j1-pad1_ Q2N2907A +r2 net-_q1-pad1_ net-_q1-pad2_ 2k +r3 net-_j1-pad1_ net-_q7-pad3_ 2.1k +q2 net-_q1-pad1_ net-_j1-pad3_ net-_q2-pad3_ Q2N2222 +q3 net-_j1-pad3_ net-_q2-pad3_ gnd Q2N2222 +d2 net-_d2-pad1_ net-_d1-pad2_ 1N4148 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q6 gnd net-_d1-pad1_ net-_d1-pad2_ Q2N2907A +q9 net-_d3-pad1_ net-_d1-pad2_ net-_q10-pad1_ Q2N2907A +q12 net-_q11-pad1_ net-_d4-pad2_ net-_q10-pad1_ Q2N2907A +q13 gnd net-_d5-pad1_ net-_d4-pad2_ Q2N2907A +d4 net-_d4-pad1_ net-_d4-pad2_ 1N4148 +d5 net-_d5-pad1_ net-_d4-pad2_ 1N4148 +r1 net-_q2-pad3_ gnd 4.8k +q11 net-_q11-pad1_ net-_d3-pad1_ gnd Q2N2222 +d3 net-_d3-pad1_ gnd 1N4148 +q14 net-_q14-pad1_ net-_q1-pad1_ net-_j1-pad1_ Q2N2907A +q15 net-_q14-pad1_ net-_q11-pad1_ gnd Q2N2222 +q16 net-_q16-pad1_ net-_q14-pad1_ gnd Q2N2222 +* u1 net-_j1-pad1_ net-_d1-pad1_ net-_d5-pad1_ net-_q16-pad1_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/LM3914/IC_LM397MFX.pro b/library/SubcircuitLibrary/LM3914/IC_LM397MFX.pro new file mode 100644 index 000000000..d7f78c3b4 --- /dev/null +++ b/library/SubcircuitLibrary/LM3914/IC_LM397MFX.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/LM3914/IC_LM397MFX.sch b/library/SubcircuitLibrary/LM3914/IC_LM397MFX.sch new file mode 100644 index 000000000..a61ecad62 --- /dev/null +++ b/library/SubcircuitLibrary/LM3914/IC_LM397MFX.sch @@ -0,0 +1,568 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:IC_LM397MFX-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L jfet_n J1 +U 1 1 6414AD39 +P 3400 3450 +F 0 "J1" H 3300 3500 50 0000 R CNN +F 1 "jfet_n" H 3350 3600 50 0000 R CNN +F 2 "" H 3600 3550 29 0000 C CNN +F 3 "" H 3400 3450 60 0000 C CNN + 1 3400 3450 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q1 +U 1 1 6414AD5B +P 3900 3100 +F 0 "Q1" H 3800 3150 50 0000 R CNN +F 1 "eSim_PNP" H 3850 3250 50 0000 R CNN +F 2 "" H 4100 3200 29 0000 C CNN +F 3 "" H 3900 3100 60 0000 C CNN + 1 3900 3100 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q4 +U 1 1 6414AD78 +P 5050 3100 +F 0 "Q4" H 4950 3150 50 0000 R CNN +F 1 "eSim_PNP" H 5000 3250 50 0000 R CNN +F 2 "" H 5250 3200 29 0000 C CNN +F 3 "" H 5050 3100 60 0000 C CNN + 1 5050 3100 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q5 +U 1 1 6414AD97 +P 5300 3500 +F 0 "Q5" H 5200 3550 50 0000 R CNN +F 1 "eSim_PNP" H 5250 3650 50 0000 R CNN +F 2 "" H 5500 3600 29 0000 C CNN +F 3 "" H 5300 3500 60 0000 C CNN + 1 5300 3500 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q8 +U 1 1 6414ADCC +P 6550 3100 +F 0 "Q8" H 6450 3150 50 0000 R CNN +F 1 "eSim_PNP" H 6500 3250 50 0000 R CNN +F 2 "" H 6750 3200 29 0000 C CNN +F 3 "" H 6550 3100 60 0000 C CNN + 1 6550 3100 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q7 +U 1 1 6414ADFD +P 6200 3500 +F 0 "Q7" H 6100 3550 50 0000 R CNN +F 1 "eSim_PNP" H 6150 3650 50 0000 R CNN +F 2 "" H 6400 3600 29 0000 C CNN +F 3 "" H 6200 3500 60 0000 C CNN + 1 6200 3500 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q10 +U 1 1 64188296 +P 7350 3100 +F 0 "Q10" H 7250 3150 50 0000 R CNN +F 1 "eSim_PNP" H 7300 3250 50 0000 R CNN +F 2 "" H 7550 3200 29 0000 C CNN +F 3 "" H 7350 3100 60 0000 C CNN + 1 7350 3100 + 1 0 0 1 +$EndComp +$Comp +L resistor R2 +U 1 1 641882BF +P 4450 3050 +F 0 "R2" H 4500 3180 50 0000 C CNN +F 1 "2k" H 4500 3000 50 0000 C CNN +F 2 "" H 4500 3030 30 0000 C CNN +F 3 "" V 4500 3100 30 0000 C CNN + 1 4450 3050 + -1 0 0 1 +$EndComp +$Comp +L resistor R3 +U 1 1 641882F4 +P 6600 2450 +F 0 "R3" H 6650 2580 50 0000 C CNN +F 1 "2.1k" H 6650 2400 50 0000 C CNN +F 2 "" H 6650 2430 30 0000 C CNN +F 3 "" V 6650 2500 30 0000 C CNN + 1 6600 2450 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 6418832D +P 3900 4600 +F 0 "Q2" H 3800 4650 50 0000 R CNN +F 1 "eSim_NPN" H 3850 4750 50 0000 R CNN +F 2 "" H 4100 4700 29 0000 C CNN +F 3 "" H 3900 4600 60 0000 C CNN + 1 3900 4600 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 6418846C +P 4550 4950 +F 0 "Q3" H 4450 5000 50 0000 R CNN +F 1 "eSim_NPN" H 4500 5100 50 0000 R CNN +F 2 "" H 4750 5050 29 0000 C CNN +F 3 "" H 4550 4950 60 0000 C CNN + 1 4550 4950 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 64188527 +P 6300 4050 +F 0 "D2" H 6300 4150 50 0000 C CNN +F 1 "eSim_Diode" H 6300 3950 50 0000 C CNN +F 2 "" H 6300 4050 60 0000 C CNN +F 3 "" H 6300 4050 60 0000 C CNN + 1 6300 4050 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 6418855E +P 5900 4300 +F 0 "D1" H 5900 4400 50 0000 C CNN +F 1 "eSim_Diode" H 5900 4200 50 0000 C CNN +F 2 "" H 5900 4300 60 0000 C CNN +F 3 "" H 5900 4300 60 0000 C CNN + 1 5900 4300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q6 +U 1 1 64188654 +P 5950 4750 +F 0 "Q6" H 5850 4800 50 0000 R CNN +F 1 "eSim_PNP" H 5900 4900 50 0000 R CNN +F 2 "" H 6150 4850 29 0000 C CNN +F 3 "" H 5950 4750 60 0000 C CNN + 1 5950 4750 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q9 +U 1 1 64188693 +P 6900 4400 +F 0 "Q9" H 6800 4450 50 0000 R CNN +F 1 "eSim_PNP" H 6850 4550 50 0000 R CNN +F 2 "" H 7100 4500 29 0000 C CNN +F 3 "" H 6900 4400 60 0000 C CNN + 1 6900 4400 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q12 +U 1 1 641886CE +P 7550 4400 +F 0 "Q12" H 7450 4450 50 0000 R CNN +F 1 "eSim_PNP" H 7500 4550 50 0000 R CNN +F 2 "" H 7750 4500 29 0000 C CNN +F 3 "" H 7550 4400 60 0000 C CNN + 1 7550 4400 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q13 +U 1 1 64188747 +P 8100 4750 +F 0 "Q13" H 8000 4800 50 0000 R CNN +F 1 "eSim_PNP" H 8050 4900 50 0000 R CNN +F 2 "" H 8300 4850 29 0000 C CNN +F 3 "" H 8100 4750 60 0000 C CNN + 1 8100 4750 + -1 0 0 1 +$EndComp +$Comp +L eSim_Diode D4 +U 1 1 64188788 +P 7950 4050 +F 0 "D4" H 7950 4150 50 0000 C CNN +F 1 "eSim_Diode" H 7950 3950 50 0000 C CNN +F 2 "" H 7950 4050 60 0000 C CNN +F 3 "" H 7950 4050 60 0000 C CNN + 1 7950 4050 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D5 +U 1 1 641887CB +P 8200 4300 +F 0 "D5" H 8200 4400 50 0000 C CNN +F 1 "eSim_Diode" H 8200 4200 50 0000 C CNN +F 2 "" H 8200 4300 60 0000 C CNN +F 3 "" H 8200 4300 60 0000 C CNN + 1 8200 4300 + -1 0 0 1 +$EndComp +$Comp +L resistor R1 +U 1 1 641891A9 +P 3750 5300 +F 0 "R1" H 3800 5430 50 0000 C CNN +F 1 "4.8k" H 3800 5250 50 0000 C CNN +F 2 "" H 3800 5280 30 0000 C CNN +F 3 "" V 3800 5350 30 0000 C CNN + 1 3750 5300 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q11 +U 1 1 6418974E +P 7350 5300 +F 0 "Q11" H 7250 5350 50 0000 R CNN +F 1 "eSim_NPN" H 7300 5450 50 0000 R CNN +F 2 "" H 7550 5400 29 0000 C CNN +F 3 "" H 7350 5300 60 0000 C CNN + 1 7350 5300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D3 +U 1 1 6418979F +P 7000 5600 +F 0 "D3" H 7000 5700 50 0000 C CNN +F 1 "eSim_Diode" H 7000 5500 50 0000 C CNN +F 2 "" H 7000 5600 60 0000 C CNN +F 3 "" H 7000 5600 60 0000 C CNN + 1 7000 5600 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q14 +U 1 1 6418A83F +P 8850 3100 +F 0 "Q14" H 8750 3150 50 0000 R CNN +F 1 "eSim_PNP" H 8800 3250 50 0000 R CNN +F 2 "" H 9050 3200 29 0000 C CNN +F 3 "" H 8850 3100 60 0000 C CNN + 1 8850 3100 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q15 +U 1 1 6418A890 +P 8900 5150 +F 0 "Q15" H 8800 5200 50 0000 R CNN +F 1 "eSim_NPN" H 8850 5300 50 0000 R CNN +F 2 "" H 9100 5250 29 0000 C CNN +F 3 "" H 8900 5150 60 0000 C CNN + 1 8900 5150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q16 +U 1 1 6418A8D7 +P 9350 4600 +F 0 "Q16" H 9250 4650 50 0000 R CNN +F 1 "eSim_NPN" H 9300 4750 50 0000 R CNN +F 2 "" H 9550 4700 29 0000 C CNN +F 3 "" H 9350 4600 60 0000 C CNN + 1 9350 4600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 6418FD2B +P 8450 1900 +F 0 "U1" H 8500 2000 30 0000 C CNN +F 1 "PORT" H 8450 1900 30 0000 C CNN +F 2 "" H 8450 1900 60 0000 C CNN +F 3 "" H 8450 1900 60 0000 C CNN + 3 8450 1900 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 6418FD82 +P 9450 1900 +F 0 "U1" H 9500 2000 30 0000 C CNN +F 1 "PORT" H 9450 1900 30 0000 C CNN +F 2 "" H 9450 1900 60 0000 C CNN +F 3 "" H 9450 1900 60 0000 C CNN + 4 9450 1900 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 6418FEFE +P 5650 1850 +F 0 "U1" H 5700 1950 30 0000 C CNN +F 1 "PORT" H 5650 1850 30 0000 C CNN +F 2 "" H 5650 1850 60 0000 C CNN +F 3 "" H 5650 1850 60 0000 C CNN + 2 5650 1850 + 0 1 1 0 +$EndComp +Wire Wire Line + 5250 3100 6350 3100 +Wire Wire Line + 5500 3100 5500 3500 +Wire Wire Line + 6000 3100 6000 3500 +Wire Wire Line + 4950 2900 5200 2900 +Wire Wire Line + 5200 2900 5200 3300 +Wire Wire Line + 6650 2900 6300 2900 +Wire Wire Line + 6300 2900 6300 3300 +Wire Wire Line + 3800 4400 3800 3300 +Wire Wire Line + 7750 4400 8000 4400 +Wire Wire Line + 8000 4400 8000 4550 +Wire Wire Line + 7950 4200 7950 4400 +Connection ~ 7950 4400 +Wire Wire Line + 8050 4300 7950 4300 +Connection ~ 7950 4300 +Wire Wire Line + 7000 4200 7450 4200 +Wire Wire Line + 6300 3700 6300 3900 +Wire Wire Line + 6050 4300 6300 4300 +Wire Wire Line + 6300 4200 6300 4550 +Wire Wire Line + 5750 4300 5650 4300 +Wire Wire Line + 5650 2100 5650 4750 +Wire Wire Line + 5650 4750 5750 4750 +Wire Wire Line + 3800 5200 3800 4800 +Wire Wire Line + 5200 3700 5200 5050 +Wire Wire Line + 5200 5050 3800 5050 +Connection ~ 3800 5050 +Wire Wire Line + 4950 3300 4950 4650 +Wire Wire Line + 4950 4650 4650 4650 +Wire Wire Line + 4650 4600 4650 4750 +Wire Wire Line + 4350 4950 4250 4950 +Wire Wire Line + 4250 4950 4250 5050 +Connection ~ 4250 5050 +Wire Wire Line + 3500 4600 4650 4600 +Connection ~ 4650 4650 +Wire Wire Line + 3500 3650 3500 4600 +Connection ~ 4100 4600 +Wire Wire Line + 4250 3100 4100 3100 +Wire Wire Line + 4550 3100 5350 3100 +Wire Wire Line + 4650 3100 4650 3400 +Wire Wire Line + 4650 3400 3800 3400 +Connection ~ 3800 3400 +Wire Wire Line + 6650 3300 6650 3550 +Wire Wire Line + 6650 3550 7950 3550 +Wire Wire Line + 7950 3550 7950 3900 +Wire Wire Line + 7450 3300 7450 4000 +Wire Wire Line + 7450 4000 7200 4000 +Wire Wire Line + 7200 4000 7200 4200 +Connection ~ 7200 4200 +Connection ~ 6000 3100 +Connection ~ 5500 3100 +Connection ~ 4650 3100 +Connection ~ 5350 3100 +Wire Wire Line + 6650 2650 6650 2900 +Wire Wire Line + 7150 3100 6200 3100 +Connection ~ 6200 3100 +Wire Wire Line + 8650 3100 7100 3100 +Connection ~ 7100 3100 +Wire Wire Line + 3500 3250 3500 2250 +Wire Wire Line + 3500 2250 8950 2250 +Wire Wire Line + 8950 2250 8950 2900 +Wire Wire Line + 6650 2350 6650 2250 +Connection ~ 6650 2250 +Wire Wire Line + 4950 2900 4950 2250 +Connection ~ 4950 2250 +Wire Wire Line + 7450 2900 7450 2250 +Connection ~ 7450 2250 +Wire Wire Line + 3800 2100 3800 2900 +Connection ~ 3800 2250 +Wire Wire Line + 8950 3300 8950 4950 +Wire Wire Line + 8950 4950 9000 4950 +Wire Wire Line + 9150 4600 8950 4600 +Connection ~ 8950 4600 +Wire Wire Line + 7450 4600 7450 5100 +Wire Wire Line + 7000 4600 7000 5450 +Wire Wire Line + 7150 5300 7000 5300 +Connection ~ 7000 5300 +Wire Wire Line + 6300 4550 6050 4550 +Connection ~ 6300 4300 +Wire Wire Line + 6700 4400 6300 4400 +Connection ~ 6300 4400 +Wire Wire Line + 3200 3450 3200 5900 +Wire Wire Line + 3200 5900 9450 5900 +Wire Wire Line + 9450 5900 9450 4800 +Wire Wire Line + 3800 5500 3800 5900 +Connection ~ 3800 5900 +Wire Wire Line + 4650 5150 4650 5900 +Connection ~ 4650 5900 +Wire Wire Line + 7000 5750 7000 5900 +Connection ~ 7000 5900 +Wire Wire Line + 6050 4950 6050 5900 +Connection ~ 6050 5900 +Wire Wire Line + 7450 5500 7450 5900 +Connection ~ 7450 5900 +Wire Wire Line + 8000 4950 8000 5900 +Connection ~ 8000 5900 +Wire Wire Line + 8700 5150 7650 5150 +Wire Wire Line + 7650 5150 7650 5000 +Wire Wire Line + 7650 5000 7450 5000 +Connection ~ 7450 5000 +Wire Wire Line + 8350 4300 8450 4300 +Wire Wire Line + 8450 2150 8450 4750 +Wire Wire Line + 8450 4750 8300 4750 +Wire Wire Line + 9000 5350 9000 5900 +Connection ~ 9000 5900 +Wire Wire Line + 9450 2150 9450 4400 +Connection ~ 8450 4300 +$Comp +L PORT U1 +U 1 1 641906E5 +P 3800 1850 +F 0 "U1" H 3850 1950 30 0000 C CNN +F 1 "PORT" H 3800 1850 30 0000 C CNN +F 2 "" H 3800 1850 60 0000 C CNN +F 3 "" H 3800 1850 60 0000 C CNN + 1 3800 1850 + 0 1 1 0 +$EndComp +$Comp +L eSim_GND #PWR01 +U 1 1 64191056 +P 6450 6100 +F 0 "#PWR01" H 6450 5850 50 0001 C CNN +F 1 "eSim_GND" H 6450 5950 50 0000 C CNN +F 2 "" H 6450 6100 50 0001 C CNN +F 3 "" H 6450 6100 50 0001 C CNN + 1 6450 6100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6450 6100 6450 5900 +Connection ~ 6450 5900 +Connection ~ 5650 4300 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/LM3914/IC_LM397MFX.sub b/library/SubcircuitLibrary/LM3914/IC_LM397MFX.sub new file mode 100644 index 000000000..c4892086c --- /dev/null +++ b/library/SubcircuitLibrary/LM3914/IC_LM397MFX.sub @@ -0,0 +1,35 @@ +* Subcircuit IC_LM397MFX +.subckt IC_LM397MFX net-_j1-pad1_ net-_d1-pad1_ net-_d5-pad1_ net-_q16-pad1_ +* c:\fossee\esim\library\subcircuitlibrary\ic_lm397mfx\ic_lm397mfx.cir +.include NPN.lib +.include D.lib +.include PNP.lib +.include NJF.lib +j1 net-_j1-pad1_ gnd net-_j1-pad3_ J2N3819 +q1 net-_q1-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q4 net-_j1-pad3_ net-_q1-pad1_ net-_j1-pad1_ Q2N2907A +q5 net-_q2-pad3_ net-_q1-pad1_ net-_j1-pad1_ Q2N2907A +q8 net-_d4-pad1_ net-_q1-pad1_ net-_q7-pad3_ Q2N2907A +q7 net-_d2-pad1_ net-_q1-pad1_ net-_q7-pad3_ Q2N2907A +q10 net-_q10-pad1_ net-_q1-pad1_ net-_j1-pad1_ Q2N2907A +r2 net-_q1-pad1_ net-_q1-pad2_ 2k +r3 net-_j1-pad1_ net-_q7-pad3_ 2.1k +q2 net-_q1-pad1_ net-_j1-pad3_ net-_q2-pad3_ Q2N2222 +q3 net-_j1-pad3_ net-_q2-pad3_ gnd Q2N2222 +d2 net-_d2-pad1_ net-_d1-pad2_ 1N4148 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q6 gnd net-_d1-pad1_ net-_d1-pad2_ Q2N2907A +q9 net-_d3-pad1_ net-_d1-pad2_ net-_q10-pad1_ Q2N2907A +q12 net-_q11-pad1_ net-_d4-pad2_ net-_q10-pad1_ Q2N2907A +q13 gnd net-_d5-pad1_ net-_d4-pad2_ Q2N2907A +d4 net-_d4-pad1_ net-_d4-pad2_ 1N4148 +d5 net-_d5-pad1_ net-_d4-pad2_ 1N4148 +r1 net-_q2-pad3_ gnd 4.8k +q11 net-_q11-pad1_ net-_d3-pad1_ gnd Q2N2222 +d3 net-_d3-pad1_ gnd 1N4148 +q14 net-_q14-pad1_ net-_q1-pad1_ net-_j1-pad1_ Q2N2907A +q15 net-_q14-pad1_ net-_q11-pad1_ gnd Q2N2222 +q16 net-_q16-pad1_ net-_q14-pad1_ gnd Q2N2222 +* Control Statements + +.ends IC_LM397MFX \ No newline at end of file diff --git a/library/SubcircuitLibrary/LM3914/IC_LM397MFX_Previous_Values.xml b/library/SubcircuitLibrary/LM3914/IC_LM397MFX_Previous_Values.xml new file mode 100644 index 000000000..4d0d8f2a7 --- /dev/null +++ b/library/SubcircuitLibrary/LM3914/IC_LM397MFX_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\JFET\NJF.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/LM3914/LM3914.cir b/library/SubcircuitLibrary/LM3914/LM3914.cir new file mode 100644 index 000000000..7432b532d --- /dev/null +++ b/library/SubcircuitLibrary/LM3914/LM3914.cir @@ -0,0 +1,102 @@ +.title KiCad schematic +U36 O_8 Net-_U35-Pad1_ adc_bridge_1 +U35 Net-_U35-Pad1_ Net-_U35-Pad2_ d_inverter +U32 mode Net-_U25-Pad1_ Net-_U32-Pad3_ d_or +X7 v+ Net-_R18-Pad1_ vin O_7 IC_LM397MFX +U42 Net-_U40-Pad2_ Net-_U42-Pad2_ Net-_U42-Pad3_ d_and +U47 Net-_U45-Pad2_ Net-_U47-Pad2_ Net-_U47-Pad3_ d_and +U49 Net-_U47-Pad3_ Net-_Q10-Pad2_ dac_bridge_1 +U1 out_1 LowEnd v+ LowEnd vin Highend unconnected-_U1-Pad7_ unconnected-_U1-Pad8_ mode out_10 out_9 out_8 out_7 out_6 out_5 out_4 out_3 out_2 PORT +Q10 out_10 Net-_Q10-Pad2_ GND eSim_NPN +R31 v+ out_10 1000 +Q9 out_9 Net-_Q9-Pad2_ GND eSim_NPN +U44 Net-_U42-Pad3_ Net-_Q9-Pad2_ dac_bridge_1 +R29 v+ out_9 1000 +X8 v+ Net-_R22-Pad1_ vin O_8 IC_LM397MFX +R21 O_8 v+ 1000 +X9 v+ Net-_R24-Pad1_ vin O_9 IC_LM397MFX +R24 Net-_R24-Pad1_ Net-_R22-Pad1_ 1000 +R27 O_10 v+ 1000 +R28 Net-_R28-Pad1_ Net-_R24-Pad1_ 1000 +R25 O_9 v+ 1000 +R22 Net-_R22-Pad1_ Net-_R18-Pad1_ 1000 +U46 O_10 Net-_U45-Pad1_ adc_bridge_1 +U40 Net-_U40-Pad1_ Net-_U40-Pad2_ d_inverter +U41 O_9 Net-_U40-Pad1_ adc_bridge_1 +U45 Net-_U45-Pad1_ Net-_U45-Pad2_ d_inverter +U48 mode Net-_U40-Pad1_ Net-_U47-Pad2_ d_or +X10 v+ Net-_R28-Pad1_ vin O_10 IC_LM397MFX +R30 LowEnd Net-_R28-Pad1_ 1000 +U37 mode Net-_U30-Pad1_ Net-_U37-Pad3_ d_or +U43 mode Net-_U35-Pad1_ Net-_U42-Pad2_ d_or +U39 Net-_U35-Pad2_ Net-_U37-Pad3_ Net-_U38-Pad1_ d_and +U38 Net-_U38-Pad1_ Net-_Q8-Pad2_ dac_bridge_1 +R23 v+ out_7 1000 +Q7 out_7 Net-_Q7-Pad2_ GND eSim_NPN +R26 v+ out_8 1000 +Q8 out_8 Net-_Q8-Pad2_ GND eSim_NPN +U33 Net-_U30-Pad2_ Net-_U32-Pad3_ Net-_U33-Pad3_ d_and +U34 Net-_U33-Pad3_ Net-_Q7-Pad2_ dac_bridge_1 +R18 Net-_R18-Pad1_ Net-_R15-Pad1_ 1000 +U21 O_5 Net-_U20-Pad1_ adc_bridge_1 +U16 O_4 Net-_U15-Pad1_ adc_bridge_1 +R14 O_5 v+ 1000 +R11 O_4 v+ 1000 +X2 v+ Net-_R4-Pad1_ vin O_2 IC_LM397MFX +X1 v+ Net-_R2-Pad1_ vin O_1 IC_LM397MFX +U4 O_1 Net-_U3-Pad1_ adc_bridge_1 +R1 O_1 v+ 1000 +U6 O_2 Net-_U13-Pad2_ adc_bridge_1 +R8 O_3 v+ 1000 +U11 O_3 Net-_U10-Pad1_ adc_bridge_1 +R5 O_2 v+ 1000 +R15 Net-_R15-Pad1_ Net-_R12-Pad1_ 1000 +R12 Net-_R12-Pad1_ Net-_R10-Pad1_ 1000 +R7 Net-_R10-Pad2_ Net-_R4-Pad1_ 1000 +X3 v+ Net-_R10-Pad2_ vin O_3 IC_LM397MFX +R10 Net-_R10-Pad1_ Net-_R10-Pad2_ 1000 +X4 v+ Net-_R10-Pad1_ vin O_4 IC_LM397MFX +X5 v+ Net-_R12-Pad1_ vin O_5 IC_LM397MFX +X6 v+ Net-_R15-Pad1_ vin O_6 IC_LM397MFX +U31 O_7 Net-_U30-Pad1_ adc_bridge_1 +U26 O_6 Net-_U25-Pad1_ adc_bridge_1 +R17 O_6 v+ 1000 +R19 O_7 v+ 1000 +R2 Net-_R2-Pad1_ Highend 1000 +R4 Net-_R4-Pad1_ Net-_R2-Pad1_ 1000 +U20 Net-_U20-Pad1_ Net-_U20-Pad2_ d_inverter +U23 mode Net-_U15-Pad1_ Net-_U23-Pad3_ d_or +U24 Net-_U20-Pad2_ Net-_U23-Pad3_ Net-_U22-Pad1_ d_and +U22 Net-_U22-Pad1_ Net-_Q5-Pad2_ dac_bridge_1 +R13 v+ out_4 1000 +Q4 out_4 Net-_Q4-Pad2_ GND eSim_NPN +R20 v+ out_6 1000 +U28 Net-_U28-Pad1_ Net-_Q6-Pad2_ dac_bridge_1 +Q6 out_6 Net-_Q6-Pad2_ GND eSim_NPN +Q5 out_5 Net-_Q5-Pad2_ GND eSim_NPN +R16 v+ out_5 1000 +U29 Net-_U25-Pad2_ Net-_U27-Pad3_ Net-_U28-Pad1_ d_and +U17 Net-_U17-Pad1_ Net-_Q4-Pad2_ dac_bridge_1 +U30 Net-_U30-Pad1_ Net-_U30-Pad2_ d_inverter +U19 Net-_U15-Pad2_ Net-_U18-Pad3_ Net-_U17-Pad1_ d_and +U3 Net-_U3-Pad1_ Net-_U2-Pad1_ d_inverter +U8 Net-_U5-Pad2_ Net-_U8-Pad2_ Net-_U7-Pad1_ d_and +U14 Net-_U10-Pad2_ Net-_U13-Pad3_ Net-_U12-Pad1_ d_and +U12 Net-_U12-Pad1_ Net-_Q3-Pad2_ dac_bridge_1 +Q3 out_3 Net-_Q3-Pad2_ GND eSim_NPN +R6 v+ out_2 1000 +R9 v+ out_3 1000 +Q2 out_2 Net-_Q2-Pad2_ GND eSim_NPN +U25 Net-_U25-Pad1_ Net-_U25-Pad2_ d_inverter +U27 mode Net-_U20-Pad1_ Net-_U27-Pad3_ d_or +U15 Net-_U15-Pad1_ Net-_U15-Pad2_ d_inverter +U13 mode Net-_U13-Pad2_ Net-_U13-Pad3_ d_or +U9 mode Net-_U3-Pad1_ Net-_U8-Pad2_ d_or +U5 Net-_U13-Pad2_ Net-_U5-Pad2_ d_inverter +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter +U18 mode Net-_U10-Pad1_ Net-_U18-Pad3_ d_or +Q1 out_1 Net-_Q1-Pad2_ GND eSim_NPN +U7 Net-_U7-Pad1_ Net-_Q2-Pad2_ dac_bridge_1 +R3 v+ out_1 1000 +U2 Net-_U2-Pad1_ Net-_Q1-Pad2_ dac_bridge_1 +.end diff --git a/library/SubcircuitLibrary/LM3914/LM3914.cir.out b/library/SubcircuitLibrary/LM3914/LM3914.cir.out new file mode 100644 index 000000000..c69516977 --- /dev/null +++ b/library/SubcircuitLibrary/LM3914/LM3914.cir.out @@ -0,0 +1,257 @@ +.title kicad schematic + +.include IC_LM397MFX.sub +.include NPN.lib +* u36 o_8 net-_u35-pad1_ adc_bridge_1 +* u35 net-_u35-pad1_ net-_u35-pad2_ d_inverter +* u32 mode net-_u25-pad1_ net-_u32-pad3_ d_or +x7 v+ net-_r18-pad1_ vin o_7 IC_LM397MFX +* u42 net-_u40-pad2_ net-_u42-pad2_ net-_u42-pad3_ d_and +* u47 net-_u45-pad2_ net-_u47-pad2_ net-_u47-pad3_ d_and +* u49 net-_u47-pad3_ net-_q10-pad2_ dac_bridge_1 +* u1 out_1 lowend v+ lowend vin highend unconnected-_u1-pad7_ unconnected-_u1-pad8_ mode out_10 out_9 out_8 out_7 out_6 out_5 out_4 out_3 out_2 port +q10 out_10 net-_q10-pad2_ gnd Q2N2222 +r31 v+ out_10 1000 +q9 out_9 net-_q9-pad2_ gnd Q2N2222 +* u44 net-_u42-pad3_ net-_q9-pad2_ dac_bridge_1 +r29 v+ out_9 1000 +x8 v+ net-_r22-pad1_ vin o_8 IC_LM397MFX +r21 o_8 v+ 1000 +x9 v+ net-_r24-pad1_ vin o_9 IC_LM397MFX +r24 net-_r24-pad1_ net-_r22-pad1_ 1000 +r27 o_10 v+ 1000 +r28 net-_r28-pad1_ net-_r24-pad1_ 1000 +r25 o_9 v+ 1000 +r22 net-_r22-pad1_ net-_r18-pad1_ 1000 +* u46 o_10 net-_u45-pad1_ adc_bridge_1 +* u40 net-_u40-pad1_ net-_u40-pad2_ d_inverter +* u41 o_9 net-_u40-pad1_ adc_bridge_1 +* u45 net-_u45-pad1_ net-_u45-pad2_ d_inverter +* u48 mode net-_u40-pad1_ net-_u47-pad2_ d_or +x10 v+ net-_r28-pad1_ vin o_10 IC_LM397MFX +r30 lowend net-_r28-pad1_ 1000 +* u37 mode net-_u30-pad1_ net-_u37-pad3_ d_or +* u43 mode net-_u35-pad1_ net-_u42-pad2_ d_or +* u39 net-_u35-pad2_ net-_u37-pad3_ net-_u38-pad1_ d_and +* u38 net-_u38-pad1_ net-_q8-pad2_ dac_bridge_1 +r23 v+ out_7 1000 +q7 out_7 net-_q7-pad2_ gnd Q2N2222 +r26 v+ out_8 1000 +q8 out_8 net-_q8-pad2_ gnd Q2N2222 +* u33 net-_u30-pad2_ net-_u32-pad3_ net-_u33-pad3_ d_and +* u34 net-_u33-pad3_ net-_q7-pad2_ dac_bridge_1 +r18 net-_r18-pad1_ net-_r15-pad1_ 1000 +* u21 o_5 net-_u20-pad1_ adc_bridge_1 +* u16 o_4 net-_u15-pad1_ adc_bridge_1 +r14 o_5 v+ 1000 +r11 o_4 v+ 1000 +x2 v+ net-_r4-pad1_ vin o_2 IC_LM397MFX +x1 v+ net-_r2-pad1_ vin o_1 IC_LM397MFX +* u4 o_1 net-_u3-pad1_ adc_bridge_1 +r1 o_1 v+ 1000 +* u6 o_2 net-_u13-pad2_ adc_bridge_1 +r8 o_3 v+ 1000 +* u11 o_3 net-_u10-pad1_ adc_bridge_1 +r5 o_2 v+ 1000 +r15 net-_r15-pad1_ net-_r12-pad1_ 1000 +r12 net-_r12-pad1_ net-_r10-pad1_ 1000 +r7 net-_r10-pad2_ net-_r4-pad1_ 1000 +x3 v+ net-_r10-pad2_ vin o_3 IC_LM397MFX +r10 net-_r10-pad1_ net-_r10-pad2_ 1000 +x4 v+ net-_r10-pad1_ vin o_4 IC_LM397MFX +x5 v+ net-_r12-pad1_ vin o_5 IC_LM397MFX +x6 v+ net-_r15-pad1_ vin o_6 IC_LM397MFX +* u31 o_7 net-_u30-pad1_ adc_bridge_1 +* u26 o_6 net-_u25-pad1_ adc_bridge_1 +r17 o_6 v+ 1000 +r19 o_7 v+ 1000 +r2 net-_r2-pad1_ highend 1000 +r4 net-_r4-pad1_ net-_r2-pad1_ 1000 +* u20 net-_u20-pad1_ net-_u20-pad2_ d_inverter +* u23 mode net-_u15-pad1_ net-_u23-pad3_ d_or +* u24 net-_u20-pad2_ net-_u23-pad3_ net-_u22-pad1_ d_and +* u22 net-_u22-pad1_ net-_q5-pad2_ dac_bridge_1 +r13 v+ out_4 1000 +q4 out_4 net-_q4-pad2_ gnd Q2N2222 +r20 v+ out_6 1000 +* u28 net-_u28-pad1_ net-_q6-pad2_ dac_bridge_1 +q6 out_6 net-_q6-pad2_ gnd Q2N2222 +q5 out_5 net-_q5-pad2_ gnd Q2N2222 +r16 v+ out_5 1000 +* u29 net-_u25-pad2_ net-_u27-pad3_ net-_u28-pad1_ d_and +* u17 net-_u17-pad1_ net-_q4-pad2_ dac_bridge_1 +* u30 net-_u30-pad1_ net-_u30-pad2_ d_inverter +* u19 net-_u15-pad2_ net-_u18-pad3_ net-_u17-pad1_ d_and +* u3 net-_u3-pad1_ net-_u2-pad1_ d_inverter +* u8 net-_u5-pad2_ net-_u8-pad2_ net-_u7-pad1_ d_and +* u14 net-_u10-pad2_ net-_u13-pad3_ net-_u12-pad1_ d_and +* u12 net-_u12-pad1_ net-_q3-pad2_ dac_bridge_1 +q3 out_3 net-_q3-pad2_ gnd Q2N2222 +r6 v+ out_2 1000 +r9 v+ out_3 1000 +q2 out_2 net-_q2-pad2_ gnd Q2N2222 +* u25 net-_u25-pad1_ net-_u25-pad2_ d_inverter +* u27 mode net-_u20-pad1_ net-_u27-pad3_ d_or +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +* u13 mode net-_u13-pad2_ net-_u13-pad3_ d_or +* u9 mode net-_u3-pad1_ net-_u8-pad2_ d_or +* u5 net-_u13-pad2_ net-_u5-pad2_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u18 mode net-_u10-pad1_ net-_u18-pad3_ d_or +q1 out_1 net-_q1-pad2_ gnd Q2N2222 +* u7 net-_u7-pad1_ net-_q2-pad2_ dac_bridge_1 +r3 v+ out_1 1000 +* u2 net-_u2-pad1_ net-_q1-pad2_ dac_bridge_1 +a1 [o_8 ] [net-_u35-pad1_ ] u36 +a2 net-_u35-pad1_ net-_u35-pad2_ u35 +a3 [mode net-_u25-pad1_ ] net-_u32-pad3_ u32 +a4 [net-_u40-pad2_ net-_u42-pad2_ ] net-_u42-pad3_ u42 +a5 [net-_u45-pad2_ net-_u47-pad2_ ] net-_u47-pad3_ u47 +a6 [net-_u47-pad3_ ] [net-_q10-pad2_ ] u49 +a7 [net-_u42-pad3_ ] [net-_q9-pad2_ ] u44 +a8 [o_10 ] [net-_u45-pad1_ ] u46 +a9 net-_u40-pad1_ net-_u40-pad2_ u40 +a10 [o_9 ] [net-_u40-pad1_ ] u41 +a11 net-_u45-pad1_ net-_u45-pad2_ u45 +a12 [mode net-_u40-pad1_ ] net-_u47-pad2_ u48 +a13 [mode net-_u30-pad1_ ] net-_u37-pad3_ u37 +a14 [mode net-_u35-pad1_ ] net-_u42-pad2_ u43 +a15 [net-_u35-pad2_ net-_u37-pad3_ ] net-_u38-pad1_ u39 +a16 [net-_u38-pad1_ ] [net-_q8-pad2_ ] u38 +a17 [net-_u30-pad2_ net-_u32-pad3_ ] net-_u33-pad3_ u33 +a18 [net-_u33-pad3_ ] [net-_q7-pad2_ ] u34 +a19 [o_5 ] [net-_u20-pad1_ ] u21 +a20 [o_4 ] [net-_u15-pad1_ ] u16 +a21 [o_1 ] [net-_u3-pad1_ ] u4 +a22 [o_2 ] [net-_u13-pad2_ ] u6 +a23 [o_3 ] [net-_u10-pad1_ ] u11 +a24 [o_7 ] [net-_u30-pad1_ ] u31 +a25 [o_6 ] [net-_u25-pad1_ ] u26 +a26 net-_u20-pad1_ net-_u20-pad2_ u20 +a27 [mode net-_u15-pad1_ ] net-_u23-pad3_ u23 +a28 [net-_u20-pad2_ net-_u23-pad3_ ] net-_u22-pad1_ u24 +a29 [net-_u22-pad1_ ] [net-_q5-pad2_ ] u22 +a30 [net-_u28-pad1_ ] [net-_q6-pad2_ ] u28 +a31 [net-_u25-pad2_ net-_u27-pad3_ ] net-_u28-pad1_ u29 +a32 [net-_u17-pad1_ ] [net-_q4-pad2_ ] u17 +a33 net-_u30-pad1_ net-_u30-pad2_ u30 +a34 [net-_u15-pad2_ net-_u18-pad3_ ] net-_u17-pad1_ u19 +a35 net-_u3-pad1_ net-_u2-pad1_ u3 +a36 [net-_u5-pad2_ net-_u8-pad2_ ] net-_u7-pad1_ u8 +a37 [net-_u10-pad2_ net-_u13-pad3_ ] net-_u12-pad1_ u14 +a38 [net-_u12-pad1_ ] [net-_q3-pad2_ ] u12 +a39 net-_u25-pad1_ net-_u25-pad2_ u25 +a40 [mode net-_u20-pad1_ ] net-_u27-pad3_ u27 +a41 net-_u15-pad1_ net-_u15-pad2_ u15 +a42 [mode net-_u13-pad2_ ] net-_u13-pad3_ u13 +a43 [mode net-_u3-pad1_ ] net-_u8-pad2_ u9 +a44 net-_u13-pad2_ net-_u5-pad2_ u5 +a45 net-_u10-pad1_ net-_u10-pad2_ u10 +a46 [mode net-_u10-pad1_ ] net-_u18-pad3_ u18 +a47 [net-_u7-pad1_ ] [net-_q2-pad2_ ] u7 +a48 [net-_u2-pad1_ ] [net-_q1-pad2_ ] u2 +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u36 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u32 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u42 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u47 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u49 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u44 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u46 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u40 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u41 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u48 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u37 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u43 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u39 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u38 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u34 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u21 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u16 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u4 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u6 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u11 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u31 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u26 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u23 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u22 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u28 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u17 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u12 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u27 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u13 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u9 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u18 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u7 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u2 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/LM3914/LM3914.kicad_sch b/library/SubcircuitLibrary/LM3914/LM3914.kicad_sch new file mode 100644 index 000000000..a943eea7b --- /dev/null +++ b/library/SubcircuitLibrary/LM3914/LM3914.kicad_sch @@ -0,0 +1,5929 @@ +(kicad_sch (version 20211123) (generator eeschema) + + (uuid 45bac54d-abb0-4b02-a676-b064adf8676d) + + (paper "A2") + + (lib_symbols + (symbol "eSim_Devices:eSim_NPN" (pin_names (offset 0) hide) (in_bom yes) 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(value "IC_LM397MFX") (footprint "") + ) + (path "/843f09da-4c01-4399-8206-6f7b9179073f" + (reference "X7") (unit 1) (value "IC_LM397MFX") (footprint "") + ) + (path "/91878eb3-c8bd-4c2d-bfdc-1ef6aa61e5e9" + (reference "X8") (unit 1) (value "IC_LM397MFX") (footprint "") + ) + (path "/7198fee7-cfdf-4fc2-89fa-0fe479db45c9" + (reference "X9") (unit 1) (value "IC_LM397MFX") (footprint "") + ) + (path "/bcf6af93-7de5-4461-b0e9-b8c6d7ab2c71" + (reference "X10") (unit 1) (value "IC_LM397MFX") (footprint "") + ) + ) +) diff --git a/library/SubcircuitLibrary/LM3914/LM3914.sub b/library/SubcircuitLibrary/LM3914/LM3914.sub new file mode 100644 index 000000000..d900db93c --- /dev/null +++ b/library/SubcircuitLibrary/LM3914/LM3914.sub @@ -0,0 +1,251 @@ +* Subcircuit LM3914 +.subckt LM3914 out_1 lowend v+ lowend vin highend unconnected-_u1-pad7_ unconnected-_u1-pad8_ mode out_10 out_9 out_8 out_7 out_6 out_5 out_4 out_3 out_2 +.title kicad schematic +.include IC_LM397MFX.sub +.include NPN.lib +* u36 o_8 net-_u35-pad1_ adc_bridge_1 +* u35 net-_u35-pad1_ net-_u35-pad2_ d_inverter +* u32 mode net-_u25-pad1_ net-_u32-pad3_ d_or +x7 v+ net-_r18-pad1_ vin o_7 IC_LM397MFX +* u42 net-_u40-pad2_ net-_u42-pad2_ net-_u42-pad3_ d_and +* u47 net-_u45-pad2_ net-_u47-pad2_ net-_u47-pad3_ d_and +* u49 net-_u47-pad3_ net-_q10-pad2_ dac_bridge_1 +q10 out_10 net-_q10-pad2_ gnd Q2N2222 +r31 v+ out_10 1000 +q9 out_9 net-_q9-pad2_ gnd Q2N2222 +* u44 net-_u42-pad3_ net-_q9-pad2_ dac_bridge_1 +r29 v+ out_9 1000 +x8 v+ net-_r22-pad1_ vin o_8 IC_LM397MFX +r21 o_8 v+ 1000 +x9 v+ net-_r24-pad1_ vin o_9 IC_LM397MFX +r24 net-_r24-pad1_ net-_r22-pad1_ 1000 +r27 o_10 v+ 1000 +r28 net-_r28-pad1_ net-_r24-pad1_ 1000 +r25 o_9 v+ 1000 +r22 net-_r22-pad1_ net-_r18-pad1_ 1000 +* u46 o_10 net-_u45-pad1_ adc_bridge_1 +* u40 net-_u40-pad1_ net-_u40-pad2_ d_inverter +* u41 o_9 net-_u40-pad1_ adc_bridge_1 +* u45 net-_u45-pad1_ net-_u45-pad2_ d_inverter +* u48 mode net-_u40-pad1_ net-_u47-pad2_ d_or +x10 v+ net-_r28-pad1_ vin o_10 IC_LM397MFX +r30 lowend net-_r28-pad1_ 1000 +* u37 mode net-_u30-pad1_ net-_u37-pad3_ d_or +* u43 mode net-_u35-pad1_ net-_u42-pad2_ d_or +* u39 net-_u35-pad2_ net-_u37-pad3_ net-_u38-pad1_ d_and +* u38 net-_u38-pad1_ net-_q8-pad2_ dac_bridge_1 +r23 v+ out_7 1000 +q7 out_7 net-_q7-pad2_ gnd Q2N2222 +r26 v+ out_8 1000 +q8 out_8 net-_q8-pad2_ gnd Q2N2222 +* u33 net-_u30-pad2_ net-_u32-pad3_ net-_u33-pad3_ d_and +* u34 net-_u33-pad3_ net-_q7-pad2_ dac_bridge_1 +r18 net-_r18-pad1_ net-_r15-pad1_ 1000 +* u21 o_5 net-_u20-pad1_ adc_bridge_1 +* u16 o_4 net-_u15-pad1_ adc_bridge_1 +r14 o_5 v+ 1000 +r11 o_4 v+ 1000 +x2 v+ net-_r4-pad1_ vin o_2 IC_LM397MFX +x1 v+ net-_r2-pad1_ vin o_1 IC_LM397MFX +* u4 o_1 net-_u3-pad1_ adc_bridge_1 +r1 o_1 v+ 1000 +* u6 o_2 net-_u13-pad2_ adc_bridge_1 +r8 o_3 v+ 1000 +* u11 o_3 net-_u10-pad1_ adc_bridge_1 +r5 o_2 v+ 1000 +r15 net-_r15-pad1_ net-_r12-pad1_ 1000 +r12 net-_r12-pad1_ net-_r10-pad1_ 1000 +r7 net-_r10-pad2_ net-_r4-pad1_ 1000 +x3 v+ net-_r10-pad2_ vin o_3 IC_LM397MFX +r10 net-_r10-pad1_ net-_r10-pad2_ 1000 +x4 v+ net-_r10-pad1_ vin o_4 IC_LM397MFX +x5 v+ net-_r12-pad1_ vin o_5 IC_LM397MFX +x6 v+ net-_r15-pad1_ vin o_6 IC_LM397MFX +* u31 o_7 net-_u30-pad1_ adc_bridge_1 +* u26 o_6 net-_u25-pad1_ adc_bridge_1 +r17 o_6 v+ 1000 +r19 o_7 v+ 1000 +r2 net-_r2-pad1_ highend 1000 +r4 net-_r4-pad1_ net-_r2-pad1_ 1000 +* u20 net-_u20-pad1_ net-_u20-pad2_ d_inverter +* u23 mode net-_u15-pad1_ net-_u23-pad3_ d_or +* u24 net-_u20-pad2_ net-_u23-pad3_ net-_u22-pad1_ d_and +* u22 net-_u22-pad1_ net-_q5-pad2_ dac_bridge_1 +r13 v+ out_4 1000 +q4 out_4 net-_q4-pad2_ gnd Q2N2222 +r20 v+ out_6 1000 +* u28 net-_u28-pad1_ net-_q6-pad2_ dac_bridge_1 +q6 out_6 net-_q6-pad2_ gnd Q2N2222 +q5 out_5 net-_q5-pad2_ gnd Q2N2222 +r16 v+ out_5 1000 +* u29 net-_u25-pad2_ net-_u27-pad3_ net-_u28-pad1_ d_and +* u17 net-_u17-pad1_ net-_q4-pad2_ dac_bridge_1 +* u30 net-_u30-pad1_ net-_u30-pad2_ d_inverter +* u19 net-_u15-pad2_ net-_u18-pad3_ net-_u17-pad1_ d_and +* u3 net-_u3-pad1_ net-_u2-pad1_ d_inverter +* u8 net-_u5-pad2_ net-_u8-pad2_ net-_u7-pad1_ d_and +* u14 net-_u10-pad2_ net-_u13-pad3_ net-_u12-pad1_ d_and +* u12 net-_u12-pad1_ net-_q3-pad2_ dac_bridge_1 +q3 out_3 net-_q3-pad2_ gnd Q2N2222 +r6 v+ out_2 1000 +r9 v+ out_3 1000 +q2 out_2 net-_q2-pad2_ gnd Q2N2222 +* u25 net-_u25-pad1_ net-_u25-pad2_ d_inverter +* u27 mode net-_u20-pad1_ net-_u27-pad3_ d_or +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +* u13 mode net-_u13-pad2_ net-_u13-pad3_ d_or +* u9 mode net-_u3-pad1_ net-_u8-pad2_ d_or +* u5 net-_u13-pad2_ net-_u5-pad2_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u18 mode net-_u10-pad1_ net-_u18-pad3_ d_or +q1 out_1 net-_q1-pad2_ gnd Q2N2222 +* u7 net-_u7-pad1_ net-_q2-pad2_ dac_bridge_1 +r3 v+ out_1 1000 +* u2 net-_u2-pad1_ net-_q1-pad2_ dac_bridge_1 +a1 [o_8 ] [net-_u35-pad1_ ] u36 +a2 net-_u35-pad1_ net-_u35-pad2_ u35 +a3 [mode net-_u25-pad1_ ] net-_u32-pad3_ u32 +a4 [net-_u40-pad2_ net-_u42-pad2_ ] net-_u42-pad3_ u42 +a5 [net-_u45-pad2_ net-_u47-pad2_ ] net-_u47-pad3_ u47 +a6 [net-_u47-pad3_ ] [net-_q10-pad2_ ] u49 +a7 [net-_u42-pad3_ ] [net-_q9-pad2_ ] u44 +a8 [o_10 ] [net-_u45-pad1_ ] u46 +a9 net-_u40-pad1_ net-_u40-pad2_ u40 +a10 [o_9 ] [net-_u40-pad1_ ] u41 +a11 net-_u45-pad1_ net-_u45-pad2_ u45 +a12 [mode net-_u40-pad1_ ] net-_u47-pad2_ u48 +a13 [mode net-_u30-pad1_ ] net-_u37-pad3_ u37 +a14 [mode net-_u35-pad1_ ] net-_u42-pad2_ u43 +a15 [net-_u35-pad2_ net-_u37-pad3_ ] net-_u38-pad1_ u39 +a16 [net-_u38-pad1_ ] [net-_q8-pad2_ ] u38 +a17 [net-_u30-pad2_ net-_u32-pad3_ ] net-_u33-pad3_ u33 +a18 [net-_u33-pad3_ ] [net-_q7-pad2_ ] u34 +a19 [o_5 ] [net-_u20-pad1_ ] u21 +a20 [o_4 ] [net-_u15-pad1_ ] u16 +a21 [o_1 ] [net-_u3-pad1_ ] u4 +a22 [o_2 ] [net-_u13-pad2_ ] u6 +a23 [o_3 ] [net-_u10-pad1_ ] u11 +a24 [o_7 ] [net-_u30-pad1_ ] u31 +a25 [o_6 ] [net-_u25-pad1_ ] u26 +a26 net-_u20-pad1_ net-_u20-pad2_ u20 +a27 [mode net-_u15-pad1_ ] net-_u23-pad3_ u23 +a28 [net-_u20-pad2_ net-_u23-pad3_ ] net-_u22-pad1_ u24 +a29 [net-_u22-pad1_ ] [net-_q5-pad2_ ] u22 +a30 [net-_u28-pad1_ ] [net-_q6-pad2_ ] u28 +a31 [net-_u25-pad2_ net-_u27-pad3_ ] net-_u28-pad1_ u29 +a32 [net-_u17-pad1_ ] [net-_q4-pad2_ ] u17 +a33 net-_u30-pad1_ net-_u30-pad2_ u30 +a34 [net-_u15-pad2_ net-_u18-pad3_ ] net-_u17-pad1_ u19 +a35 net-_u3-pad1_ net-_u2-pad1_ u3 +a36 [net-_u5-pad2_ net-_u8-pad2_ ] net-_u7-pad1_ u8 +a37 [net-_u10-pad2_ net-_u13-pad3_ ] net-_u12-pad1_ u14 +a38 [net-_u12-pad1_ ] [net-_q3-pad2_ ] u12 +a39 net-_u25-pad1_ net-_u25-pad2_ u25 +a40 [mode net-_u20-pad1_ ] net-_u27-pad3_ u27 +a41 net-_u15-pad1_ net-_u15-pad2_ u15 +a42 [mode net-_u13-pad2_ ] net-_u13-pad3_ u13 +a43 [mode net-_u3-pad1_ ] net-_u8-pad2_ u9 +a44 net-_u13-pad2_ net-_u5-pad2_ u5 +a45 net-_u10-pad1_ net-_u10-pad2_ u10 +a46 [mode net-_u10-pad1_ ] net-_u18-pad3_ u18 +a47 [net-_u7-pad1_ ] [net-_q2-pad2_ ] u7 +a48 [net-_u2-pad1_ ] [net-_q1-pad2_ ] u2 +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u36 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u32 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u42 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u47 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u49 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u44 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u46 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u40 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u41 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u48 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u37 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u43 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u39 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u38 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u34 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u21 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u16 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u4 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u6 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u11 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u31 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u26 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u23 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u22 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u28 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u17 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u12 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u27 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u13 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u9 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u18 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u7 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u2 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Control Statements + +.ends LM3914 \ No newline at end of file diff --git a/library/SubcircuitLibrary/LM3914/LM3914_Previous_Values.xml b/library/SubcircuitLibrary/LM3914/LM3914_Previous_Values.xml new file mode 100644 index 000000000..48c812ddb --- /dev/null +++ b/library/SubcircuitLibrary/LM3914/LM3914_Previous_Values.xml @@ -0,0 +1 @@ +adc_bridged_inverterd_ord_andd_anddac_bridgedac_bridgeadc_bridged_inverteradc_bridged_inverterd_ord_ord_ord_anddac_bridged_anddac_bridgeadc_bridgeadc_bridgeadc_bridgeadc_bridgeadc_bridgeadc_bridgeadc_bridged_inverterd_ord_anddac_bridgedac_bridged_anddac_bridged_inverterd_andd_inverterd_andd_anddac_bridged_inverterd_ord_inverterd_ord_ord_inverterd_inverterd_ordac_bridgedac_bridgeC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\SubcircuitLibrary\IC_LM397MFXC:\FOSSEE\eSim\library\SubcircuitLibrary\IC_LM397MFXC:\FOSSEE\eSim\library\SubcircuitLibrary\IC_LM397MFXC:\FOSSEE\eSim\library\SubcircuitLibrary\IC_LM397MFXC:\FOSSEE\eSim\library\SubcircuitLibrary\IC_LM397MFXC:\FOSSEE\eSim\library\SubcircuitLibrary\IC_LM397MFXC:\FOSSEE\eSim\library\SubcircuitLibrary\IC_LM397MFXC:\FOSSEE\eSim\library\SubcircuitLibrary\IC_LM397MFXC:\FOSSEE\eSim\library\SubcircuitLibrary\IC_LM397MFXC:\FOSSEE\eSim\library\SubcircuitLibrary\IC_LM397MFXtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/LM3914/NJF.lib b/library/SubcircuitLibrary/LM3914/NJF.lib new file mode 100644 index 000000000..dbb2cbae5 --- /dev/null +++ b/library/SubcircuitLibrary/LM3914/NJF.lib @@ -0,0 +1,4 @@ +.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) diff --git a/library/SubcircuitLibrary/LM3914/NPN.lib b/library/SubcircuitLibrary/LM3914/NPN.lib new file mode 100644 index 000000000..be5f3073a --- /dev/null +++ b/library/SubcircuitLibrary/LM3914/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/LM3914/PNP.lib b/library/SubcircuitLibrary/LM3914/PNP.lib new file mode 100644 index 000000000..7edda0eab --- /dev/null +++ b/library/SubcircuitLibrary/LM3914/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/LM3914/README.md b/library/SubcircuitLibrary/LM3914/README.md new file mode 100644 index 000000000..b2107de03 --- /dev/null +++ b/library/SubcircuitLibrary/LM3914/README.md @@ -0,0 +1,16 @@ + +# IC_LM397MFX IC + +LM397MFX is a Single General-Purpose Voltage Comparator IC. + + +## Documentation + +To know the details of LM397MFX IC please go through with the documentation : [LM397MFX_datasheet](https://www.ti.com/lit/ds/symlink/lm397.pdf?ts=1690183083144&ref_url=https%253A%252F%252Fwww.google.com%252F) + + +## Contributer + +Name: Hrittika Ghosh +Year: 2023 +Position: FOSSEE Winter Intern 2023 diff --git a/library/SubcircuitLibrary/LM3914/Schematic.pdf b/library/SubcircuitLibrary/LM3914/Schematic.pdf new file mode 100644 index 000000000..fd6d3472b Binary files /dev/null and b/library/SubcircuitLibrary/LM3914/Schematic.pdf differ diff --git a/library/SubcircuitLibrary/LM3914/analysis b/library/SubcircuitLibrary/LM3914/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/LM3914/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/MM74C923/#auto_saved_files# b/library/SubcircuitLibrary/MM74C923/#auto_saved_files# new file mode 100644 index 000000000..a91a20fc9 --- /dev/null +++ b/library/SubcircuitLibrary/MM74C923/#auto_saved_files# @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\SubcircuitLibrary\MM74C923\_autosave-MM74C923.sch diff --git a/library/SubcircuitLibrary/MM74C923/MM74C923.cir b/library/SubcircuitLibrary/MM74C923/MM74C923.cir new file mode 100644 index 000000000..7377c680f --- /dev/null +++ b/library/SubcircuitLibrary/MM74C923/MM74C923.cir @@ -0,0 +1,60 @@ +.title KiCad schematic +U1 Y1 Y2 Y3 Y4 Y5 clk unconnected-_U1-Pad7_ X4 X3 unconnected-_U1-Pad10_ X2 X1 data_available Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ Net-_U1-Pad19_ unconnected-_U1-Pad20_ PORT +U17 Net-_U16-Pad3_ X2 d_inverter +U6 Net-_U2-Pad1_ Net-_U18-Pad2_ Net-_U6-Pad3_ d_and +U16 Net-_U16-Pad1_ Net-_U15-Pad5_ Net-_U16-Pad3_ d_and +U8 Net-_U6-Pad3_ X3 d_inverter +U10 Y3 d_pullup +U13 Y1 d_pullup +U14 Y2 d_pullup +U5 Net-_U4-Pad2_ Net-_U15-Pad1_ d_inverter +U9 GND Net-_U15-Pad3_ adc_bridge_1 +U4 GND Net-_U4-Pad2_ adc_bridge_1 +U15 Net-_U15-Pad1_ Net-_U15-Pad2_ Net-_U15-Pad3_ Net-_U15-Pad4_ Net-_U15-Pad5_ unconnected-_U15-Pad6_ d_tff +U7 GND Net-_U15-Pad4_ adc_bridge_1 +U21 Net-_U15-Pad5_ Net-_U15-Pad2_ Net-_U15-Pad3_ Net-_U15-Pad4_ Net-_U2-Pad1_ unconnected-_U21-Pad6_ d_tff +U40 GND Net-_U40-Pad2_ adc_bridge_1 +U18 Net-_U15-Pad5_ Net-_U18-Pad2_ d_inverter +U19 Net-_U16-Pad1_ Net-_U18-Pad2_ Net-_U19-Pad3_ d_and +U20 Net-_U19-Pad3_ X1 d_inverter +U3 Net-_U2-Pad3_ X4 d_inverter +U2 Net-_U2-Pad1_ Net-_U15-Pad5_ Net-_U2-Pad3_ d_and +U24 Y3 Net-_U24-Pad2_ Net-_U23-Pad2_ d_and +U25 Y4 Y5 Net-_U24-Pad2_ d_and +U31 Y5 Net-_U31-Pad2_ d_inverter +U22 Y1 Net-_U22-Pad2_ Net-_U22-Pad3_ d_and +U23 Y2 Net-_U23-Pad2_ Net-_U22-Pad2_ d_and +U12 Y5 d_pullup +U11 Y4 d_pullup +U46 Net-_U38-Pad3_ Net-_U41-Pad2_ Net-_U40-Pad2_ Net-_U42-Pad2_ Net-_U46-Pad5_ unconnected-_U46-Pad6_ d_dff +U45 Net-_U39-Pad3_ Net-_U41-Pad2_ Net-_U40-Pad2_ Net-_U42-Pad2_ Net-_U45-Pad5_ unconnected-_U45-Pad6_ d_dff +U53 Net-_U47-Pad5_ Net-_U48-Pad2_ Net-_U1-Pad15_ d_and +U58 Net-_U1-Pad15_ E dac_bridge_1 +U35 clk Net-_U32-Pad2_ adc_bridge_1 +U32 Net-_U22-Pad3_ Net-_U32-Pad2_ Net-_U15-Pad2_ d_and +U26 Net-_U2-Pad1_ Net-_U16-Pad1_ d_inverter +U37 Net-_U22-Pad3_ data_available dac_bridge_1 +U43 Net-_U15-Pad5_ Net-_U41-Pad2_ Net-_U40-Pad2_ Net-_U42-Pad2_ Net-_U43-Pad5_ unconnected-_U43-Pad6_ d_dff +U44 Net-_U2-Pad1_ Net-_U41-Pad2_ Net-_U40-Pad2_ Net-_U42-Pad2_ Net-_U44-Pad5_ unconnected-_U44-Pad6_ d_dff +U28 Y2 Net-_U28-Pad2_ d_inverter +U27 Y1 unconnected-_U27-Pad2_ d_inverter +U30 Y4 Net-_U30-Pad2_ d_inverter +U29 Y3 Net-_U29-Pad2_ d_inverter +U33 Net-_U28-Pad2_ Y3 Net-_U33-Pad3_ d_and +U36 Net-_U33-Pad3_ Net-_U30-Pad2_ Net-_U36-Pad3_ d_or +U34 Net-_U29-Pad2_ Net-_U30-Pad2_ Net-_U34-Pad3_ d_or +U38 Net-_U34-Pad3_ Y5 Net-_U38-Pad3_ d_and +U39 Net-_U36-Pad3_ Y5 Net-_U39-Pad3_ d_and +U48 Net-_U1-Pad14_ Net-_U48-Pad2_ d_inverter +U47 Net-_U31-Pad2_ Net-_U41-Pad2_ Net-_U40-Pad2_ Net-_U42-Pad2_ Net-_U47-Pad5_ unconnected-_U47-Pad6_ d_dff +U42 GND Net-_U42-Pad2_ adc_bridge_1 +U41 Net-_U22-Pad3_ Net-_U41-Pad2_ d_inverter +U50 Net-_U43-Pad5_ Net-_U48-Pad2_ Net-_U1-Pad19_ d_and +U51 Net-_U44-Pad5_ Net-_U48-Pad2_ Net-_U1-Pad18_ d_and +U54 Net-_U1-Pad19_ A dac_bridge_1 +U56 Net-_U1-Pad18_ B dac_bridge_1 +U57 Net-_U1-Pad16_ D dac_bridge_1 +U52 Net-_U46-Pad5_ Net-_U48-Pad2_ Net-_U1-Pad16_ d_and +U49 Net-_U45-Pad5_ Net-_U48-Pad2_ Net-_U1-Pad17_ d_and +U55 Net-_U1-Pad17_ C dac_bridge_1 +.end diff --git a/library/SubcircuitLibrary/MM74C923/MM74C923.cir.out b/library/SubcircuitLibrary/MM74C923/MM74C923.cir.out new file mode 100644 index 000000000..21456fa8e --- /dev/null +++ b/library/SubcircuitLibrary/MM74C923/MM74C923.cir.out @@ -0,0 +1,240 @@ +.title kicad schematic + +* u1 y1 y2 y3 y4 y5 clk unconnected-_u1-pad7_ x4 x3 unconnected-_u1-pad10_ x2 x1 data_available net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ unconnected-_u1-pad20_ port +* u17 net-_u16-pad3_ x2 d_inverter +* u6 net-_u2-pad1_ net-_u18-pad2_ net-_u6-pad3_ d_and +* u16 net-_u16-pad1_ net-_u15-pad5_ net-_u16-pad3_ d_and +* u8 net-_u6-pad3_ x3 d_inverter +* u10 y3 d_pullup +* u13 y1 d_pullup +* u14 y2 d_pullup +* u5 net-_u4-pad2_ net-_u15-pad1_ d_inverter +* u9 gnd net-_u15-pad3_ adc_bridge_1 +* u4 gnd net-_u4-pad2_ adc_bridge_1 +* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ net-_u15-pad4_ net-_u15-pad5_ unconnected-_u15-pad6_ d_tff +* u7 gnd net-_u15-pad4_ adc_bridge_1 +* u21 net-_u15-pad5_ net-_u15-pad2_ net-_u15-pad3_ net-_u15-pad4_ net-_u2-pad1_ unconnected-_u21-pad6_ d_tff +* u40 gnd net-_u40-pad2_ adc_bridge_1 +* u18 net-_u15-pad5_ net-_u18-pad2_ d_inverter +* u19 net-_u16-pad1_ net-_u18-pad2_ net-_u19-pad3_ d_and +* u20 net-_u19-pad3_ x1 d_inverter +* u3 net-_u2-pad3_ x4 d_inverter +* u2 net-_u2-pad1_ net-_u15-pad5_ net-_u2-pad3_ d_and +* u24 y3 net-_u24-pad2_ net-_u23-pad2_ d_and +* u25 y4 y5 net-_u24-pad2_ d_and +* u31 y5 net-_u31-pad2_ d_inverter +* u22 y1 net-_u22-pad2_ net-_u22-pad3_ d_and +* u23 y2 net-_u23-pad2_ net-_u22-pad2_ d_and +* u12 y5 d_pullup +* u11 y4 d_pullup +* u46 net-_u38-pad3_ net-_u41-pad2_ net-_u40-pad2_ net-_u42-pad2_ net-_u46-pad5_ unconnected-_u46-pad6_ d_dff +* u45 net-_u39-pad3_ net-_u41-pad2_ net-_u40-pad2_ net-_u42-pad2_ net-_u45-pad5_ unconnected-_u45-pad6_ d_dff +* u53 net-_u47-pad5_ net-_u48-pad2_ net-_u1-pad15_ d_and +* u58 net-_u1-pad15_ e dac_bridge_1 +* u35 clk net-_u32-pad2_ adc_bridge_1 +* u32 net-_u22-pad3_ net-_u32-pad2_ net-_u15-pad2_ d_and +* u26 net-_u2-pad1_ net-_u16-pad1_ d_inverter +* u37 net-_u22-pad3_ data_available dac_bridge_1 +* u43 net-_u15-pad5_ net-_u41-pad2_ net-_u40-pad2_ net-_u42-pad2_ net-_u43-pad5_ unconnected-_u43-pad6_ d_dff +* u44 net-_u2-pad1_ net-_u41-pad2_ net-_u40-pad2_ net-_u42-pad2_ net-_u44-pad5_ unconnected-_u44-pad6_ d_dff +* u28 y2 net-_u28-pad2_ d_inverter +* u27 y1 unconnected-_u27-pad2_ d_inverter +* u30 y4 net-_u30-pad2_ d_inverter +* u29 y3 net-_u29-pad2_ d_inverter +* u33 net-_u28-pad2_ y3 net-_u33-pad3_ d_and +* u36 net-_u33-pad3_ net-_u30-pad2_ net-_u36-pad3_ d_or +* u34 net-_u29-pad2_ net-_u30-pad2_ net-_u34-pad3_ d_or +* u38 net-_u34-pad3_ y5 net-_u38-pad3_ d_and +* u39 net-_u36-pad3_ y5 net-_u39-pad3_ d_and +* u48 net-_u1-pad14_ net-_u48-pad2_ d_inverter +* u47 net-_u31-pad2_ net-_u41-pad2_ net-_u40-pad2_ net-_u42-pad2_ net-_u47-pad5_ unconnected-_u47-pad6_ d_dff +* u42 gnd net-_u42-pad2_ adc_bridge_1 +* u41 net-_u22-pad3_ net-_u41-pad2_ d_inverter +* u50 net-_u43-pad5_ net-_u48-pad2_ net-_u1-pad19_ d_and +* u51 net-_u44-pad5_ net-_u48-pad2_ net-_u1-pad18_ d_and +* u54 net-_u1-pad19_ a dac_bridge_1 +* u56 net-_u1-pad18_ b dac_bridge_1 +* u57 net-_u1-pad16_ d dac_bridge_1 +* u52 net-_u46-pad5_ net-_u48-pad2_ net-_u1-pad16_ d_and +* u49 net-_u45-pad5_ net-_u48-pad2_ net-_u1-pad17_ d_and +* u55 net-_u1-pad17_ c dac_bridge_1 +a1 net-_u16-pad3_ x2 u17 +a2 [net-_u2-pad1_ net-_u18-pad2_ ] net-_u6-pad3_ u6 +a3 [net-_u16-pad1_ net-_u15-pad5_ ] net-_u16-pad3_ u16 +a4 net-_u6-pad3_ x3 u8 +a5 y3 u10 +a6 y1 u13 +a7 y2 u14 +a8 net-_u4-pad2_ net-_u15-pad1_ u5 +a9 [gnd ] [net-_u15-pad3_ ] u9 +a10 [gnd ] [net-_u4-pad2_ ] u4 +a11 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ net-_u15-pad4_ net-_u15-pad5_ unconnected-_u15-pad6_ u15 +a12 [gnd ] [net-_u15-pad4_ ] u7 +a13 net-_u15-pad5_ net-_u15-pad2_ net-_u15-pad3_ net-_u15-pad4_ net-_u2-pad1_ unconnected-_u21-pad6_ u21 +a14 [gnd ] [net-_u40-pad2_ ] u40 +a15 net-_u15-pad5_ net-_u18-pad2_ u18 +a16 [net-_u16-pad1_ net-_u18-pad2_ ] net-_u19-pad3_ u19 +a17 net-_u19-pad3_ x1 u20 +a18 net-_u2-pad3_ x4 u3 +a19 [net-_u2-pad1_ net-_u15-pad5_ ] net-_u2-pad3_ u2 +a20 [y3 net-_u24-pad2_ ] net-_u23-pad2_ u24 +a21 [y4 y5 ] net-_u24-pad2_ u25 +a22 y5 net-_u31-pad2_ u31 +a23 [y1 net-_u22-pad2_ ] net-_u22-pad3_ u22 +a24 [y2 net-_u23-pad2_ ] net-_u22-pad2_ u23 +a25 y5 u12 +a26 y4 u11 +a27 net-_u38-pad3_ net-_u41-pad2_ net-_u40-pad2_ net-_u42-pad2_ net-_u46-pad5_ unconnected-_u46-pad6_ u46 +a28 net-_u39-pad3_ net-_u41-pad2_ net-_u40-pad2_ net-_u42-pad2_ net-_u45-pad5_ unconnected-_u45-pad6_ u45 +a29 [net-_u47-pad5_ net-_u48-pad2_ ] net-_u1-pad15_ u53 +a30 [net-_u1-pad15_ ] [e ] u58 +a31 [clk ] [net-_u32-pad2_ ] u35 +a32 [net-_u22-pad3_ net-_u32-pad2_ ] net-_u15-pad2_ u32 +a33 net-_u2-pad1_ net-_u16-pad1_ u26 +a34 [net-_u22-pad3_ ] [data_available ] u37 +a35 net-_u15-pad5_ net-_u41-pad2_ net-_u40-pad2_ net-_u42-pad2_ net-_u43-pad5_ unconnected-_u43-pad6_ u43 +a36 net-_u2-pad1_ net-_u41-pad2_ net-_u40-pad2_ net-_u42-pad2_ net-_u44-pad5_ unconnected-_u44-pad6_ u44 +a37 y2 net-_u28-pad2_ u28 +a38 y1 unconnected-_u27-pad2_ u27 +a39 y4 net-_u30-pad2_ u30 +a40 y3 net-_u29-pad2_ u29 +a41 [net-_u28-pad2_ y3 ] net-_u33-pad3_ u33 +a42 [net-_u33-pad3_ net-_u30-pad2_ ] net-_u36-pad3_ u36 +a43 [net-_u29-pad2_ net-_u30-pad2_ ] net-_u34-pad3_ u34 +a44 [net-_u34-pad3_ y5 ] net-_u38-pad3_ u38 +a45 [net-_u36-pad3_ y5 ] net-_u39-pad3_ u39 +a46 net-_u1-pad14_ net-_u48-pad2_ u48 +a47 net-_u31-pad2_ net-_u41-pad2_ net-_u40-pad2_ net-_u42-pad2_ net-_u47-pad5_ unconnected-_u47-pad6_ u47 +a48 [gnd ] [net-_u42-pad2_ ] u42 +a49 net-_u22-pad3_ net-_u41-pad2_ u41 +a50 [net-_u43-pad5_ net-_u48-pad2_ ] net-_u1-pad19_ u50 +a51 [net-_u44-pad5_ net-_u48-pad2_ ] net-_u1-pad18_ u51 +a52 [net-_u1-pad19_ ] [a ] u54 +a53 [net-_u1-pad18_ ] [b ] u56 +a54 [net-_u1-pad16_ ] [d ] u57 +a55 [net-_u46-pad5_ net-_u48-pad2_ ] net-_u1-pad16_ u52 +a56 [net-_u45-pad5_ net-_u48-pad2_ ] net-_u1-pad17_ u49 +a57 [net-_u1-pad17_ ] [c ] u55 +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_pullup, Ngspice Name: d_pullup +.model u10 d_pullup(load=1.0e-12 ) +* Schematic Name: d_pullup, Ngspice Name: d_pullup +.model u13 d_pullup(load=1.0e-12 ) +* Schematic Name: d_pullup, Ngspice Name: d_pullup +.model u14 d_pullup(load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u9 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u4 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tff, Ngspice Name: d_tff +.model u15 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u7 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tff, Ngspice Name: d_tff +.model u21 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u40 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_pullup, Ngspice Name: d_pullup +.model u12 d_pullup(load=1.0e-12 ) +* Schematic Name: d_pullup, Ngspice Name: d_pullup +.model u11 d_pullup(load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u46 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u45 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u53 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u58 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u35 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u37 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u43 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u44 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u36 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u34 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u39 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u48 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u47 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u42 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u41 d_inverter(rise_delay=1u fall_delay=1u input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u50 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u51 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u54 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u56 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u57 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u52 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u49 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u55 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/MM74C923/MM74C923.kicad_sch b/library/SubcircuitLibrary/MM74C923/MM74C923.kicad_sch new file mode 100644 index 000000000..0d12bd955 --- /dev/null +++ b/library/SubcircuitLibrary/MM74C923/MM74C923.kicad_sch @@ -0,0 +1,4061 @@ +(kicad_sch (version 20211123) (generator eeschema) + + (uuid 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"U38") (unit 1) (value "d_and") (footprint "") + ) + (path "/01983019-5a68-4003-a940-a0a788893ded" + (reference "U39") (unit 1) (value "d_and") (footprint "") + ) + (path "/8565b283-f29a-4c2f-8b7d-3bc74ce840ef" + (reference "U40") (unit 1) (value "adc_bridge_1") (footprint "") + ) + (path "/e2181aa3-fbde-45ab-b60e-3464a1caa5a1" + (reference "U41") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/ad199d14-90ee-45c3-8497-0b91327b89df" + (reference "U42") (unit 1) (value "adc_bridge_1") (footprint "") + ) + (path "/e7fd088e-cab6-4de7-9517-ac6b212cf241" + (reference "U43") (unit 1) (value "d_dff") (footprint "") + ) + (path "/9cb472b0-362a-4e69-b284-e9cedb47fcd1" + (reference "U44") (unit 1) (value "d_dff") (footprint "") + ) + (path "/7c22d621-b427-49f4-81d8-f633c434400f" + (reference "U45") (unit 1) (value "d_dff") (footprint "") + ) + (path "/59543f48-6751-4a56-9bfa-423b10c14999" + (reference "U46") (unit 1) (value "d_dff") (footprint "") + ) + (path "/9117d5be-0365-4202-a188-f917d4624071" + (reference "U47") (unit 1) (value "d_dff") (footprint "") + ) + (path "/79f20e4b-1243-4fbf-9975-da7489aeca8c" + (reference "U48") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/03895cbe-95f4-4c7b-895c-59d5fc511f29" + (reference "U49") (unit 1) (value "d_and") (footprint "") + ) + (path "/a1b95dc8-17ce-4205-a364-38c424191b5a" + (reference "U50") (unit 1) (value "d_and") (footprint "") + ) + (path "/d733c11f-60d6-467a-8540-0e4a4f7c0dc7" + (reference "U51") (unit 1) (value "d_and") (footprint "") + ) + (path "/34532151-f163-4726-b842-f4236fbee621" + (reference "U52") (unit 1) (value "d_and") (footprint "") + ) + (path "/0d8d231b-5412-461f-8c16-77f06eadab4c" + (reference "U53") (unit 1) (value "d_and") (footprint "") + ) + (path "/1e51334b-afa0-431d-a76e-5bededa4d5cc" + (reference "U54") (unit 1) (value "dac_bridge_1") (footprint "") + ) + (path "/d066e937-04ac-47e9-bafe-12720fbf6e77" + (reference "U55") (unit 1) (value "dac_bridge_1") (footprint "") + ) + (path "/9dc787a9-2441-4a2d-a3b3-c35c06e93090" + (reference "U56") (unit 1) (value "dac_bridge_1") (footprint "") + ) + (path "/7e259a3b-b0f5-4e2a-8b6c-001a04100e51" + (reference "U57") (unit 1) (value "dac_bridge_1") (footprint "") + ) + (path "/2572bbe5-afb4-4adb-8523-35329b15e730" + (reference "U58") (unit 1) (value "dac_bridge_1") (footprint "") + ) + ) +) diff --git a/library/SubcircuitLibrary/MM74C923/MM74C923.sub b/library/SubcircuitLibrary/MM74C923/MM74C923.sub new file mode 100644 index 000000000..7b2f73966 --- /dev/null +++ b/library/SubcircuitLibrary/MM74C923/MM74C923.sub @@ -0,0 +1,234 @@ +* Subcircuit MM74C923 +.subckt MM74C923 y1 y2 y3 y4 y5 clk unconnected-_u1-pad7_ x4 x3 unconnected-_u1-pad10_ x2 x1 data_available net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ unconnected-_u1-pad20_ +.title kicad schematic +* u17 net-_u16-pad3_ x2 d_inverter +* u6 net-_u2-pad1_ net-_u18-pad2_ net-_u6-pad3_ d_and +* u16 net-_u16-pad1_ net-_u15-pad5_ net-_u16-pad3_ d_and +* u8 net-_u6-pad3_ x3 d_inverter +* u10 y3 d_pullup +* u13 y1 d_pullup +* u14 y2 d_pullup +* u5 net-_u4-pad2_ net-_u15-pad1_ d_inverter +* u9 gnd net-_u15-pad3_ adc_bridge_1 +* u4 gnd net-_u4-pad2_ adc_bridge_1 +* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ net-_u15-pad4_ net-_u15-pad5_ unconnected-_u15-pad6_ d_tff +* u7 gnd net-_u15-pad4_ adc_bridge_1 +* u21 net-_u15-pad5_ net-_u15-pad2_ net-_u15-pad3_ net-_u15-pad4_ net-_u2-pad1_ unconnected-_u21-pad6_ d_tff +* u40 gnd net-_u40-pad2_ adc_bridge_1 +* u18 net-_u15-pad5_ net-_u18-pad2_ d_inverter +* u19 net-_u16-pad1_ net-_u18-pad2_ net-_u19-pad3_ d_and +* u20 net-_u19-pad3_ x1 d_inverter +* u3 net-_u2-pad3_ x4 d_inverter +* u2 net-_u2-pad1_ net-_u15-pad5_ net-_u2-pad3_ d_and +* u24 y3 net-_u24-pad2_ net-_u23-pad2_ d_and +* u25 y4 y5 net-_u24-pad2_ d_and +* u31 y5 net-_u31-pad2_ d_inverter +* u22 y1 net-_u22-pad2_ net-_u22-pad3_ d_and +* u23 y2 net-_u23-pad2_ net-_u22-pad2_ d_and +* u12 y5 d_pullup +* u11 y4 d_pullup +* u46 net-_u38-pad3_ net-_u41-pad2_ net-_u40-pad2_ net-_u42-pad2_ net-_u46-pad5_ unconnected-_u46-pad6_ d_dff +* u45 net-_u39-pad3_ net-_u41-pad2_ net-_u40-pad2_ net-_u42-pad2_ net-_u45-pad5_ unconnected-_u45-pad6_ d_dff +* u53 net-_u47-pad5_ net-_u48-pad2_ net-_u1-pad15_ d_and +* u58 net-_u1-pad15_ e dac_bridge_1 +* u35 clk net-_u32-pad2_ adc_bridge_1 +* u32 net-_u22-pad3_ net-_u32-pad2_ net-_u15-pad2_ d_and +* u26 net-_u2-pad1_ net-_u16-pad1_ d_inverter +* u37 net-_u22-pad3_ data_available dac_bridge_1 +* u43 net-_u15-pad5_ net-_u41-pad2_ net-_u40-pad2_ net-_u42-pad2_ net-_u43-pad5_ unconnected-_u43-pad6_ d_dff +* u44 net-_u2-pad1_ net-_u41-pad2_ net-_u40-pad2_ net-_u42-pad2_ net-_u44-pad5_ unconnected-_u44-pad6_ d_dff +* u28 y2 net-_u28-pad2_ d_inverter +* u27 y1 unconnected-_u27-pad2_ d_inverter +* u30 y4 net-_u30-pad2_ d_inverter +* u29 y3 net-_u29-pad2_ d_inverter +* u33 net-_u28-pad2_ y3 net-_u33-pad3_ d_and +* u36 net-_u33-pad3_ net-_u30-pad2_ net-_u36-pad3_ d_or +* u34 net-_u29-pad2_ net-_u30-pad2_ net-_u34-pad3_ d_or +* u38 net-_u34-pad3_ y5 net-_u38-pad3_ d_and +* u39 net-_u36-pad3_ y5 net-_u39-pad3_ d_and +* u48 net-_u1-pad14_ net-_u48-pad2_ d_inverter +* u47 net-_u31-pad2_ net-_u41-pad2_ net-_u40-pad2_ net-_u42-pad2_ net-_u47-pad5_ unconnected-_u47-pad6_ d_dff +* u42 gnd net-_u42-pad2_ adc_bridge_1 +* u41 net-_u22-pad3_ net-_u41-pad2_ d_inverter +* u50 net-_u43-pad5_ net-_u48-pad2_ net-_u1-pad19_ d_and +* u51 net-_u44-pad5_ net-_u48-pad2_ net-_u1-pad18_ d_and +* u54 net-_u1-pad19_ a dac_bridge_1 +* u56 net-_u1-pad18_ b dac_bridge_1 +* u57 net-_u1-pad16_ d dac_bridge_1 +* u52 net-_u46-pad5_ net-_u48-pad2_ net-_u1-pad16_ d_and +* u49 net-_u45-pad5_ net-_u48-pad2_ net-_u1-pad17_ d_and +* u55 net-_u1-pad17_ c dac_bridge_1 +a1 net-_u16-pad3_ x2 u17 +a2 [net-_u2-pad1_ net-_u18-pad2_ ] net-_u6-pad3_ u6 +a3 [net-_u16-pad1_ net-_u15-pad5_ ] net-_u16-pad3_ u16 +a4 net-_u6-pad3_ x3 u8 +a5 y3 u10 +a6 y1 u13 +a7 y2 u14 +a8 net-_u4-pad2_ net-_u15-pad1_ u5 +a9 [gnd ] [net-_u15-pad3_ ] u9 +a10 [gnd ] [net-_u4-pad2_ ] u4 +a11 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ net-_u15-pad4_ net-_u15-pad5_ unconnected-_u15-pad6_ u15 +a12 [gnd ] [net-_u15-pad4_ ] u7 +a13 net-_u15-pad5_ net-_u15-pad2_ net-_u15-pad3_ net-_u15-pad4_ net-_u2-pad1_ unconnected-_u21-pad6_ u21 +a14 [gnd ] [net-_u40-pad2_ ] u40 +a15 net-_u15-pad5_ net-_u18-pad2_ u18 +a16 [net-_u16-pad1_ net-_u18-pad2_ ] net-_u19-pad3_ u19 +a17 net-_u19-pad3_ x1 u20 +a18 net-_u2-pad3_ x4 u3 +a19 [net-_u2-pad1_ net-_u15-pad5_ ] net-_u2-pad3_ u2 +a20 [y3 net-_u24-pad2_ ] net-_u23-pad2_ u24 +a21 [y4 y5 ] net-_u24-pad2_ u25 +a22 y5 net-_u31-pad2_ u31 +a23 [y1 net-_u22-pad2_ ] net-_u22-pad3_ u22 +a24 [y2 net-_u23-pad2_ ] net-_u22-pad2_ u23 +a25 y5 u12 +a26 y4 u11 +a27 net-_u38-pad3_ net-_u41-pad2_ net-_u40-pad2_ net-_u42-pad2_ net-_u46-pad5_ unconnected-_u46-pad6_ u46 +a28 net-_u39-pad3_ net-_u41-pad2_ net-_u40-pad2_ net-_u42-pad2_ net-_u45-pad5_ unconnected-_u45-pad6_ u45 +a29 [net-_u47-pad5_ net-_u48-pad2_ ] net-_u1-pad15_ u53 +a30 [net-_u1-pad15_ ] [e ] u58 +a31 [clk ] [net-_u32-pad2_ ] u35 +a32 [net-_u22-pad3_ net-_u32-pad2_ ] net-_u15-pad2_ u32 +a33 net-_u2-pad1_ net-_u16-pad1_ u26 +a34 [net-_u22-pad3_ ] [data_available ] u37 +a35 net-_u15-pad5_ net-_u41-pad2_ net-_u40-pad2_ net-_u42-pad2_ net-_u43-pad5_ unconnected-_u43-pad6_ u43 +a36 net-_u2-pad1_ net-_u41-pad2_ net-_u40-pad2_ net-_u42-pad2_ net-_u44-pad5_ unconnected-_u44-pad6_ u44 +a37 y2 net-_u28-pad2_ u28 +a38 y1 unconnected-_u27-pad2_ u27 +a39 y4 net-_u30-pad2_ u30 +a40 y3 net-_u29-pad2_ u29 +a41 [net-_u28-pad2_ y3 ] net-_u33-pad3_ u33 +a42 [net-_u33-pad3_ net-_u30-pad2_ ] net-_u36-pad3_ u36 +a43 [net-_u29-pad2_ net-_u30-pad2_ ] net-_u34-pad3_ u34 +a44 [net-_u34-pad3_ y5 ] net-_u38-pad3_ u38 +a45 [net-_u36-pad3_ y5 ] net-_u39-pad3_ u39 +a46 net-_u1-pad14_ net-_u48-pad2_ u48 +a47 net-_u31-pad2_ net-_u41-pad2_ net-_u40-pad2_ net-_u42-pad2_ net-_u47-pad5_ unconnected-_u47-pad6_ u47 +a48 [gnd ] [net-_u42-pad2_ ] u42 +a49 net-_u22-pad3_ net-_u41-pad2_ u41 +a50 [net-_u43-pad5_ net-_u48-pad2_ ] net-_u1-pad19_ u50 +a51 [net-_u44-pad5_ net-_u48-pad2_ ] net-_u1-pad18_ u51 +a52 [net-_u1-pad19_ ] [a ] u54 +a53 [net-_u1-pad18_ ] [b ] u56 +a54 [net-_u1-pad16_ ] [d ] u57 +a55 [net-_u46-pad5_ net-_u48-pad2_ ] net-_u1-pad16_ u52 +a56 [net-_u45-pad5_ net-_u48-pad2_ ] net-_u1-pad17_ u49 +a57 [net-_u1-pad17_ ] [c ] u55 +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_pullup, Ngspice Name: d_pullup +.model u10 d_pullup(load=1.0e-12 ) +* Schematic Name: d_pullup, Ngspice Name: d_pullup +.model u13 d_pullup(load=1.0e-12 ) +* Schematic Name: d_pullup, Ngspice Name: d_pullup +.model u14 d_pullup(load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u9 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u4 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tff, Ngspice Name: d_tff +.model u15 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u7 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tff, Ngspice Name: d_tff +.model u21 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u40 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_pullup, Ngspice Name: d_pullup +.model u12 d_pullup(load=1.0e-12 ) +* Schematic Name: d_pullup, Ngspice Name: d_pullup +.model u11 d_pullup(load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u46 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u45 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u53 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u58 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u35 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u37 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u43 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u44 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u36 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u34 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u39 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u48 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, Ngspice Name: d_dff +.model u47 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u42 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u41 d_inverter(rise_delay=1u fall_delay=1u input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u50 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u51 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u54 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u56 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u57 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u52 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u49 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, Ngspice Name: dac_bridge +.model u55 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Control Statements + +.ends MM74C923 \ No newline at end of file diff --git a/library/SubcircuitLibrary/MM74C923/MM74C923_Previous_Values.xml b/library/SubcircuitLibrary/MM74C923/MM74C923_Previous_Values.xml new file mode 100644 index 000000000..4629620ae --- /dev/null +++ b/library/SubcircuitLibrary/MM74C923/MM74C923_Previous_Values.xml @@ -0,0 +1 @@ +d_inverterd_andd_andd_inverterd_pullupd_pullupd_pullupd_inverteradc_bridgeadc_bridged_tffadc_bridged_tffadc_bridged_inverterd_andd_inverterd_inverterd_andd_andd_andd_inverterd_andd_andd_pullupd_pullupd_dffd_dffd_anddac_bridgeadc_bridged_andd_inverterdac_bridged_dffd_dffd_inverterd_inverterd_inverterd_inverterd_andd_ord_ord_andd_andd_inverterd_dffadc_bridged_inverter1u1ud_andd_anddac_bridgedac_bridgedac_bridged_andd_anddac_bridgetruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/MM74C923/_autosave-MM74C923.sch b/library/SubcircuitLibrary/MM74C923/_autosave-MM74C923.sch new file mode 100644 index 000000000..ac10e4cdc --- /dev/null +++ b/library/SubcircuitLibrary/MM74C923/_autosave-MM74C923.sch @@ -0,0 +1,1470 @@ +EESchema Schematic File Version 5 +EELAYER 36 0 +EELAYER END +$Descr A1 33110 23386 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" 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H 10780 7050 60 0000 L CNN +F 1 "d_tff" H 10780 6900 60 0000 L CNN +F 2 "" H 10700 6400 60 0000 C CNN +F 3 "" H 10700 6400 60 0000 C CNN + 1 10700 6400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_dff U43 +U 1 1 00000000 +P 18400 6450 +F 0 "U43" H 18480 7100 60 0000 L CNN +F 1 "d_dff" H 18480 6950 60 0000 L CNN +F 2 "" H 18400 6450 60 0000 C CNN +F 3 "" H 18400 6450 60 0000 C CNN + 1 18400 6450 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_dff U44 +U 1 1 00000000 +P 18400 8000 +F 0 "U44" H 18480 8650 60 0000 L CNN +F 1 "d_dff" H 18480 8500 60 0000 L CNN +F 2 "" H 18400 8000 60 0000 C CNN +F 3 "" H 18400 8000 60 0000 C CNN + 1 18400 8000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_dff U45 +U 1 1 00000000 +P 18400 9600 +F 0 "U45" H 18480 10250 60 0000 L CNN +F 1 "d_dff" H 18480 10100 60 0000 L CNN +F 2 "" H 18400 9600 60 0000 C CNN +F 3 "" H 18400 9600 60 0000 C CNN + 1 18400 9600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_dff U46 +U 1 1 00000000 +P 18400 11250 +F 0 "U46" H 18480 11900 60 0000 L CNN +F 1 "d_dff" H 18480 11750 60 0000 L CNN +F 2 "" H 18400 11250 60 0000 C CNN +F 3 "" H 18400 11250 60 0000 C CNN + 1 18400 11250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_dff U47 +U 1 1 00000000 +P 18400 12950 +F 0 "U47" H 18480 13600 60 0000 L CNN +F 1 "d_dff" H 18480 13450 60 0000 L CNN +F 2 "" H 18400 12950 60 0000 C CNN +F 3 "" H 18400 12950 60 0000 C CNN + 1 18400 12950 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/MM74C923/analysis b/library/SubcircuitLibrary/MM74C923/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/MM74C923/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54170/SN54170.cir b/library/SubcircuitLibrary/SN54170/SN54170.cir new file mode 100644 index 000000000..2e231a1b5 --- /dev/null +++ b/library/SubcircuitLibrary/SN54170/SN54170.cir @@ -0,0 +1,102 @@ +.title KiCad schematic +U50 Net-_U50-Pad1_ RB Net-_U34-Pad1_ d_and +U54 RA Net-_U50-Pad1_ d_inverter +U77 Net-_U61-Pad1_ Net-_U61-Pad2_ Net-_U73-Pad2_ d_and +U78 Net-_U62-Pad1_ Net-_U62-Pad2_ Net-_U74-Pad2_ d_and +U58 D1 Net-_U58-Pad2_ Net-_U55-Pad2_ Net-_U100-Pad2_ Net-_U45-Pad2_ unconnected-_U58-Pad6_ d_dlatch +U74 D3 Net-_U74-Pad2_ Net-_U55-Pad2_ Net-_U100-Pad2_ Net-_U41-Pad2_ unconnected-_U74-Pad6_ d_dlatch +U66 D2 Net-_U66-Pad2_ Net-_U55-Pad2_ Net-_U100-Pad2_ Net-_U44-Pad2_ unconnected-_U66-Pad6_ d_dlatch +U69 Net-_U61-Pad1_ Net-_U61-Pad2_ Net-_U65-Pad2_ d_and +U61 Net-_U61-Pad1_ Net-_U61-Pad2_ Net-_U57-Pad2_ d_and +U57 D1 Net-_U57-Pad2_ Net-_U55-Pad2_ Net-_U100-Pad2_ Net-_U39-Pad2_ unconnected-_U57-Pad6_ d_dlatch +U60 Net-_U60-Pad1_ Net-_U60-Pad2_ Net-_U56-Pad2_ d_and +U56 D1 Net-_U56-Pad2_ Net-_U55-Pad2_ Net-_U100-Pad2_ Net-_U33-Pad2_ unconnected-_U56-Pad6_ d_dlatch +U49 RA RB Net-_U30-Pad1_ d_and +U68 Net-_U60-Pad1_ Net-_U60-Pad2_ Net-_U64-Pad2_ d_and +U65 D2 Net-_U65-Pad2_ Net-_U55-Pad2_ Net-_U100-Pad2_ Net-_U38-Pad2_ unconnected-_U65-Pad6_ d_dlatch +U73 D3 Net-_U73-Pad2_ Net-_U55-Pad2_ Net-_U100-Pad2_ Net-_U35-Pad2_ unconnected-_U73-Pad6_ d_dlatch +U76 Net-_U60-Pad1_ Net-_U60-Pad2_ Net-_U72-Pad2_ d_and +U64 D2 Net-_U64-Pad2_ Net-_U55-Pad2_ Net-_U100-Pad2_ Net-_U32-Pad2_ unconnected-_U64-Pad6_ d_dlatch +U72 D3 Net-_U72-Pad2_ Net-_U55-Pad2_ Net-_U100-Pad2_ Net-_U31-Pad2_ unconnected-_U72-Pad6_ d_dlatch +U1 D2 D3 D4 RB RA Q4 Q3 GND Q2 Q1 Gr_bar Gw_bar WB WA D1 unconnected-_U1-Pad16_ PORT +U46 Gr_bar Net-_U14-Pad1_ d_inverter +U55 GND Net-_U55-Pad2_ adc_bridge_1 +U52 RB Net-_U47-Pad2_ d_inverter +U51 RA Net-_U47-Pad1_ d_inverter +U63 Net-_U63-Pad1_ Net-_U63-Pad2_ Net-_U59-Pad2_ d_and +U67 D2 Net-_U67-Pad2_ Net-_U55-Pad2_ Net-_U100-Pad2_ Net-_U42-Pad2_ unconnected-_U67-Pad6_ d_dlatch +U71 Net-_U63-Pad1_ Net-_U63-Pad2_ Net-_U67-Pad2_ d_and +U70 Net-_U62-Pad1_ Net-_U62-Pad2_ Net-_U66-Pad2_ d_and +U59 D1 Net-_U59-Pad2_ Net-_U55-Pad2_ Net-_U100-Pad2_ Net-_U43-Pad2_ unconnected-_U59-Pad6_ d_dlatch +U62 Net-_U62-Pad1_ Net-_U62-Pad2_ Net-_U58-Pad2_ d_and +U53 RB Net-_U48-Pad2_ d_inverter +U48 RA Net-_U48-Pad2_ Net-_U40-Pad1_ d_and +U47 Net-_U47-Pad1_ Net-_U47-Pad2_ Net-_U36-Pad1_ d_and +U22 Net-_U14-Pad1_ Net-_U22-Pad2_ Net-_U22-Pad3_ d_and +U35 Net-_U34-Pad1_ Net-_U35-Pad2_ Net-_U19-Pad2_ d_and +U34 Net-_U34-Pad1_ Net-_U34-Pad2_ Net-_U18-Pad2_ d_and +U18 Net-_U14-Pad1_ Net-_U18-Pad2_ Net-_U13-Pad1_ d_and +U19 Net-_U14-Pad1_ Net-_U19-Pad2_ Net-_U10-Pad1_ d_and +U39 Net-_U34-Pad1_ Net-_U39-Pad2_ Net-_U23-Pad2_ d_and +U38 Net-_U34-Pad1_ Net-_U38-Pad2_ Net-_U22-Pad2_ d_and +U33 Net-_U30-Pad1_ Net-_U33-Pad2_ Net-_U17-Pad2_ d_and +U30 Net-_U30-Pad1_ Net-_U30-Pad2_ Net-_U14-Pad2_ d_and +U15 Net-_U14-Pad1_ Net-_U15-Pad2_ Net-_U10-Pad2_ d_and +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U13-Pad2_ d_and +U31 Net-_U30-Pad1_ Net-_U31-Pad2_ Net-_U15-Pad2_ d_and +U32 Net-_U30-Pad1_ Net-_U32-Pad2_ Net-_U16-Pad2_ d_and +U17 Net-_U14-Pad1_ Net-_U17-Pad2_ Net-_U17-Pad3_ d_and +U16 Net-_U14-Pad1_ Net-_U16-Pad2_ Net-_U16-Pad3_ d_and +U45 Net-_U40-Pad1_ Net-_U45-Pad2_ Net-_U29-Pad2_ d_and +U24 Net-_U14-Pad1_ Net-_U24-Pad2_ Net-_U12-Pad2_ d_and +U41 Net-_U40-Pad1_ Net-_U41-Pad2_ Net-_U25-Pad2_ d_and +U44 Net-_U40-Pad1_ Net-_U44-Pad2_ Net-_U28-Pad2_ d_and +U98 WA Net-_U95-Pad1_ d_inverter +U99 WB Net-_U95-Pad2_ d_inverter +U95 Net-_U95-Pad1_ Net-_U95-Pad2_ Net-_U63-Pad2_ d_and +U88 Gw_bar Net-_U63-Pad1_ d_inverter +U100 GND Net-_U100-Pad2_ adc_bridge_1 +U79 Net-_U63-Pad1_ Net-_U63-Pad2_ Net-_U75-Pad2_ d_and +U75 D3 Net-_U75-Pad2_ Net-_U55-Pad2_ Net-_U100-Pad2_ Net-_U37-Pad2_ unconnected-_U75-Pad6_ d_dlatch +U87 Net-_U63-Pad1_ Net-_U63-Pad2_ Net-_U83-Pad2_ d_and +U80 D4 Net-_U80-Pad2_ Net-_U55-Pad2_ Net-_U100-Pad2_ Net-_U30-Pad2_ unconnected-_U80-Pad6_ d_dlatch +U84 Net-_U60-Pad1_ Net-_U60-Pad2_ Net-_U80-Pad2_ d_and +U81 D4 Net-_U81-Pad2_ Net-_U55-Pad2_ Net-_U100-Pad2_ Net-_U34-Pad2_ unconnected-_U81-Pad6_ d_dlatch +U82 D4 Net-_U82-Pad2_ Net-_U55-Pad2_ Net-_U100-Pad2_ Net-_U40-Pad2_ unconnected-_U82-Pad6_ d_dlatch +U86 Net-_U62-Pad1_ Net-_U62-Pad2_ Net-_U82-Pad2_ d_and +U83 D4 Net-_U83-Pad2_ Net-_U55-Pad2_ Net-_U100-Pad2_ Net-_U36-Pad2_ unconnected-_U83-Pad6_ d_dlatch +U97 WB Net-_U94-Pad2_ d_inverter +U93 Gw_bar Net-_U62-Pad1_ d_inverter +U94 WA Net-_U94-Pad2_ Net-_U62-Pad2_ d_and +U96 WA Net-_U92-Pad1_ d_inverter +U92 Net-_U92-Pad1_ WB Net-_U61-Pad2_ d_and +U85 Net-_U61-Pad1_ Net-_U61-Pad2_ Net-_U81-Pad2_ d_and +U90 WA WB Net-_U60-Pad2_ d_and +U89 Gw_bar Net-_U60-Pad1_ d_inverter +U91 Gw_bar Net-_U61-Pad1_ d_inverter +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_xor +U6 Net-_U6-Pad1_ Net-_U10-Pad3_ Q3 d_xor +U8 Net-_U21-Pad3_ Net-_U25-Pad3_ Net-_U6-Pad1_ d_xor +U9 Net-_U22-Pad3_ Net-_U16-Pad3_ Net-_U5-Pad2_ d_xor +U7 Net-_U26-Pad3_ Net-_U28-Pad3_ Net-_U5-Pad1_ d_xor +U5 Net-_U5-Pad1_ Net-_U5-Pad2_ Q2 d_xor +U40 Net-_U40-Pad1_ Net-_U40-Pad2_ Net-_U24-Pad2_ d_and +U23 Net-_U14-Pad1_ Net-_U23-Pad2_ Net-_U23-Pad3_ d_and +U2 Net-_U2-Pad1_ Net-_U2-Pad2_ Q1 d_xor +U4 Net-_U23-Pad3_ Net-_U17-Pad3_ Net-_U2-Pad2_ d_xor +U3 Net-_U27-Pad3_ Net-_U29-Pad3_ Net-_U2-Pad1_ d_xor +U29 Net-_U14-Pad1_ Net-_U29-Pad2_ Net-_U29-Pad3_ d_and +U25 Net-_U14-Pad1_ Net-_U25-Pad2_ Net-_U25-Pad3_ d_and +U28 Net-_U14-Pad1_ Net-_U28-Pad2_ Net-_U28-Pad3_ d_and +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U11-Pad1_ d_xor +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Q4 d_xor +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U11-Pad2_ d_xor +U27 Net-_U14-Pad1_ Net-_U27-Pad2_ Net-_U27-Pad3_ d_and +U42 Net-_U36-Pad1_ Net-_U42-Pad2_ Net-_U26-Pad2_ d_and +U36 Net-_U36-Pad1_ Net-_U36-Pad2_ Net-_U20-Pad2_ d_and +U37 Net-_U36-Pad1_ Net-_U37-Pad2_ Net-_U21-Pad2_ d_and +U43 Net-_U36-Pad1_ Net-_U43-Pad2_ Net-_U27-Pad2_ d_and +U26 Net-_U14-Pad1_ Net-_U26-Pad2_ Net-_U26-Pad3_ d_and +U21 Net-_U14-Pad1_ Net-_U21-Pad2_ Net-_U21-Pad3_ d_and +U20 Net-_U14-Pad1_ Net-_U20-Pad2_ Net-_U12-Pad1_ d_and +.end diff --git a/library/SubcircuitLibrary/SN54170/SN54170.cir.out b/library/SubcircuitLibrary/SN54170/SN54170.cir.out new file mode 100644 index 000000000..5ab9732a6 --- /dev/null +++ b/library/SubcircuitLibrary/SN54170/SN54170.cir.out @@ -0,0 +1,408 @@ +.title kicad schematic + +* u50 net-_u50-pad1_ rb net-_u34-pad1_ d_and +* u54 ra net-_u50-pad1_ d_inverter +* u77 net-_u61-pad1_ net-_u61-pad2_ net-_u73-pad2_ d_and +* u78 net-_u62-pad1_ net-_u62-pad2_ net-_u74-pad2_ d_and +* u58 d1 net-_u58-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u45-pad2_ unconnected-_u58-pad6_ d_dlatch +* u74 d3 net-_u74-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u41-pad2_ unconnected-_u74-pad6_ d_dlatch +* u66 d2 net-_u66-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u44-pad2_ unconnected-_u66-pad6_ d_dlatch +* u69 net-_u61-pad1_ net-_u61-pad2_ net-_u65-pad2_ d_and +* u61 net-_u61-pad1_ net-_u61-pad2_ net-_u57-pad2_ d_and +* u57 d1 net-_u57-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u39-pad2_ unconnected-_u57-pad6_ d_dlatch +* u60 net-_u60-pad1_ net-_u60-pad2_ net-_u56-pad2_ d_and +* u56 d1 net-_u56-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u33-pad2_ unconnected-_u56-pad6_ d_dlatch +* u49 ra rb net-_u30-pad1_ d_and +* u68 net-_u60-pad1_ net-_u60-pad2_ net-_u64-pad2_ d_and +* u65 d2 net-_u65-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u38-pad2_ unconnected-_u65-pad6_ d_dlatch +* u73 d3 net-_u73-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u35-pad2_ unconnected-_u73-pad6_ d_dlatch +* u76 net-_u60-pad1_ net-_u60-pad2_ net-_u72-pad2_ d_and +* u64 d2 net-_u64-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u32-pad2_ unconnected-_u64-pad6_ d_dlatch +* u72 d3 net-_u72-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u31-pad2_ unconnected-_u72-pad6_ d_dlatch +* u1 d2 d3 d4 rb ra q4 q3 gnd q2 q1 gr_bar gw_bar wb wa d1 unconnected-_u1-pad16_ port +* u46 gr_bar net-_u14-pad1_ d_inverter +* u55 gnd net-_u55-pad2_ adc_bridge_1 +* u52 rb net-_u47-pad2_ d_inverter +* u51 ra net-_u47-pad1_ d_inverter +* u63 net-_u63-pad1_ net-_u63-pad2_ net-_u59-pad2_ d_and +* u67 d2 net-_u67-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u42-pad2_ unconnected-_u67-pad6_ d_dlatch +* u71 net-_u63-pad1_ net-_u63-pad2_ net-_u67-pad2_ d_and +* u70 net-_u62-pad1_ net-_u62-pad2_ net-_u66-pad2_ d_and +* u59 d1 net-_u59-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u43-pad2_ unconnected-_u59-pad6_ d_dlatch +* u62 net-_u62-pad1_ net-_u62-pad2_ net-_u58-pad2_ d_and +* u53 rb net-_u48-pad2_ d_inverter +* u48 ra net-_u48-pad2_ net-_u40-pad1_ d_and +* u47 net-_u47-pad1_ net-_u47-pad2_ net-_u36-pad1_ d_and +* u22 net-_u14-pad1_ net-_u22-pad2_ net-_u22-pad3_ d_and +* u35 net-_u34-pad1_ net-_u35-pad2_ net-_u19-pad2_ d_and +* u34 net-_u34-pad1_ net-_u34-pad2_ net-_u18-pad2_ d_and +* u18 net-_u14-pad1_ net-_u18-pad2_ net-_u13-pad1_ d_and +* u19 net-_u14-pad1_ net-_u19-pad2_ net-_u10-pad1_ d_and +* u39 net-_u34-pad1_ net-_u39-pad2_ net-_u23-pad2_ d_and +* u38 net-_u34-pad1_ net-_u38-pad2_ net-_u22-pad2_ d_and +* u33 net-_u30-pad1_ net-_u33-pad2_ net-_u17-pad2_ d_and +* u30 net-_u30-pad1_ net-_u30-pad2_ net-_u14-pad2_ d_and +* u15 net-_u14-pad1_ net-_u15-pad2_ net-_u10-pad2_ d_and +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u13-pad2_ d_and +* u31 net-_u30-pad1_ net-_u31-pad2_ net-_u15-pad2_ d_and +* u32 net-_u30-pad1_ net-_u32-pad2_ net-_u16-pad2_ d_and +* u17 net-_u14-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_and +* u16 net-_u14-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_and +* u45 net-_u40-pad1_ net-_u45-pad2_ net-_u29-pad2_ d_and +* u24 net-_u14-pad1_ net-_u24-pad2_ net-_u12-pad2_ d_and +* u41 net-_u40-pad1_ net-_u41-pad2_ net-_u25-pad2_ d_and +* u44 net-_u40-pad1_ net-_u44-pad2_ net-_u28-pad2_ d_and +* u98 wa net-_u95-pad1_ d_inverter +* u99 wb net-_u95-pad2_ d_inverter +* u95 net-_u95-pad1_ net-_u95-pad2_ net-_u63-pad2_ d_and +* u88 gw_bar net-_u63-pad1_ d_inverter +* u100 gnd net-_u100-pad2_ adc_bridge_1 +* u79 net-_u63-pad1_ net-_u63-pad2_ net-_u75-pad2_ d_and +* u75 d3 net-_u75-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u37-pad2_ unconnected-_u75-pad6_ d_dlatch +* u87 net-_u63-pad1_ net-_u63-pad2_ net-_u83-pad2_ d_and +* u80 d4 net-_u80-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u30-pad2_ unconnected-_u80-pad6_ d_dlatch +* u84 net-_u60-pad1_ net-_u60-pad2_ net-_u80-pad2_ d_and +* u81 d4 net-_u81-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u34-pad2_ unconnected-_u81-pad6_ d_dlatch +* u82 d4 net-_u82-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u40-pad2_ unconnected-_u82-pad6_ d_dlatch +* u86 net-_u62-pad1_ net-_u62-pad2_ net-_u82-pad2_ d_and +* u83 d4 net-_u83-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u36-pad2_ unconnected-_u83-pad6_ d_dlatch +* u97 wb net-_u94-pad2_ d_inverter +* u93 gw_bar net-_u62-pad1_ d_inverter +* u94 wa net-_u94-pad2_ net-_u62-pad2_ d_and +* u96 wa net-_u92-pad1_ d_inverter +* u92 net-_u92-pad1_ wb net-_u61-pad2_ d_and +* u85 net-_u61-pad1_ net-_u61-pad2_ net-_u81-pad2_ d_and +* u90 wa wb net-_u60-pad2_ d_and +* u89 gw_bar net-_u60-pad1_ d_inverter +* u91 gw_bar net-_u61-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_xor +* u6 net-_u6-pad1_ net-_u10-pad3_ q3 d_xor +* u8 net-_u21-pad3_ net-_u25-pad3_ net-_u6-pad1_ d_xor +* u9 net-_u22-pad3_ net-_u16-pad3_ net-_u5-pad2_ d_xor +* u7 net-_u26-pad3_ net-_u28-pad3_ net-_u5-pad1_ d_xor +* u5 net-_u5-pad1_ net-_u5-pad2_ q2 d_xor +* u40 net-_u40-pad1_ net-_u40-pad2_ net-_u24-pad2_ d_and +* u23 net-_u14-pad1_ net-_u23-pad2_ net-_u23-pad3_ d_and +* u2 net-_u2-pad1_ net-_u2-pad2_ q1 d_xor +* u4 net-_u23-pad3_ net-_u17-pad3_ net-_u2-pad2_ d_xor +* u3 net-_u27-pad3_ net-_u29-pad3_ net-_u2-pad1_ d_xor +* u29 net-_u14-pad1_ net-_u29-pad2_ net-_u29-pad3_ d_and +* u25 net-_u14-pad1_ net-_u25-pad2_ net-_u25-pad3_ d_and +* u28 net-_u14-pad1_ net-_u28-pad2_ net-_u28-pad3_ d_and +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u11-pad1_ d_xor +* u11 net-_u11-pad1_ net-_u11-pad2_ q4 d_xor +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u11-pad2_ d_xor +* u27 net-_u14-pad1_ net-_u27-pad2_ net-_u27-pad3_ d_and +* u42 net-_u36-pad1_ net-_u42-pad2_ net-_u26-pad2_ d_and +* u36 net-_u36-pad1_ net-_u36-pad2_ net-_u20-pad2_ d_and +* u37 net-_u36-pad1_ net-_u37-pad2_ net-_u21-pad2_ d_and +* u43 net-_u36-pad1_ net-_u43-pad2_ net-_u27-pad2_ d_and +* u26 net-_u14-pad1_ net-_u26-pad2_ net-_u26-pad3_ d_and +* u21 net-_u14-pad1_ net-_u21-pad2_ net-_u21-pad3_ d_and +* u20 net-_u14-pad1_ net-_u20-pad2_ net-_u12-pad1_ d_and +a1 [net-_u50-pad1_ rb ] net-_u34-pad1_ u50 +a2 ra net-_u50-pad1_ u54 +a3 [net-_u61-pad1_ net-_u61-pad2_ ] net-_u73-pad2_ u77 +a4 [net-_u62-pad1_ net-_u62-pad2_ ] net-_u74-pad2_ u78 +a5 d1 net-_u58-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u45-pad2_ unconnected-_u58-pad6_ u58 +a6 d3 net-_u74-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u41-pad2_ unconnected-_u74-pad6_ u74 +a7 d2 net-_u66-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u44-pad2_ unconnected-_u66-pad6_ u66 +a8 [net-_u61-pad1_ net-_u61-pad2_ ] net-_u65-pad2_ u69 +a9 [net-_u61-pad1_ net-_u61-pad2_ ] net-_u57-pad2_ u61 +a10 d1 net-_u57-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u39-pad2_ unconnected-_u57-pad6_ u57 +a11 [net-_u60-pad1_ net-_u60-pad2_ ] net-_u56-pad2_ u60 +a12 d1 net-_u56-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u33-pad2_ unconnected-_u56-pad6_ u56 +a13 [ra rb ] net-_u30-pad1_ u49 +a14 [net-_u60-pad1_ net-_u60-pad2_ ] net-_u64-pad2_ u68 +a15 d2 net-_u65-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u38-pad2_ unconnected-_u65-pad6_ u65 +a16 d3 net-_u73-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u35-pad2_ unconnected-_u73-pad6_ u73 +a17 [net-_u60-pad1_ net-_u60-pad2_ ] net-_u72-pad2_ u76 +a18 d2 net-_u64-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u32-pad2_ unconnected-_u64-pad6_ u64 +a19 d3 net-_u72-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u31-pad2_ unconnected-_u72-pad6_ u72 +a20 gr_bar net-_u14-pad1_ u46 +a21 [gnd ] [net-_u55-pad2_ ] u55 +a22 rb net-_u47-pad2_ u52 +a23 ra net-_u47-pad1_ u51 +a24 [net-_u63-pad1_ net-_u63-pad2_ ] net-_u59-pad2_ u63 +a25 d2 net-_u67-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u42-pad2_ unconnected-_u67-pad6_ u67 +a26 [net-_u63-pad1_ net-_u63-pad2_ ] net-_u67-pad2_ u71 +a27 [net-_u62-pad1_ net-_u62-pad2_ ] net-_u66-pad2_ u70 +a28 d1 net-_u59-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u43-pad2_ unconnected-_u59-pad6_ u59 +a29 [net-_u62-pad1_ net-_u62-pad2_ ] net-_u58-pad2_ u62 +a30 rb net-_u48-pad2_ u53 +a31 [ra net-_u48-pad2_ ] net-_u40-pad1_ u48 +a32 [net-_u47-pad1_ net-_u47-pad2_ ] net-_u36-pad1_ u47 +a33 [net-_u14-pad1_ net-_u22-pad2_ ] net-_u22-pad3_ u22 +a34 [net-_u34-pad1_ net-_u35-pad2_ ] net-_u19-pad2_ u35 +a35 [net-_u34-pad1_ net-_u34-pad2_ ] net-_u18-pad2_ u34 +a36 [net-_u14-pad1_ net-_u18-pad2_ ] net-_u13-pad1_ u18 +a37 [net-_u14-pad1_ net-_u19-pad2_ ] net-_u10-pad1_ u19 +a38 [net-_u34-pad1_ net-_u39-pad2_ ] net-_u23-pad2_ u39 +a39 [net-_u34-pad1_ net-_u38-pad2_ ] net-_u22-pad2_ u38 +a40 [net-_u30-pad1_ net-_u33-pad2_ ] net-_u17-pad2_ u33 +a41 [net-_u30-pad1_ net-_u30-pad2_ ] net-_u14-pad2_ u30 +a42 [net-_u14-pad1_ net-_u15-pad2_ ] net-_u10-pad2_ u15 +a43 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u13-pad2_ u14 +a44 [net-_u30-pad1_ net-_u31-pad2_ ] net-_u15-pad2_ u31 +a45 [net-_u30-pad1_ net-_u32-pad2_ ] net-_u16-pad2_ u32 +a46 [net-_u14-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17 +a47 [net-_u14-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16 +a48 [net-_u40-pad1_ net-_u45-pad2_ ] net-_u29-pad2_ u45 +a49 [net-_u14-pad1_ net-_u24-pad2_ ] net-_u12-pad2_ u24 +a50 [net-_u40-pad1_ net-_u41-pad2_ ] net-_u25-pad2_ u41 +a51 [net-_u40-pad1_ net-_u44-pad2_ ] net-_u28-pad2_ u44 +a52 wa net-_u95-pad1_ u98 +a53 wb net-_u95-pad2_ u99 +a54 [net-_u95-pad1_ net-_u95-pad2_ ] net-_u63-pad2_ u95 +a55 gw_bar net-_u63-pad1_ u88 +a56 [gnd ] [net-_u100-pad2_ ] u100 +a57 [net-_u63-pad1_ net-_u63-pad2_ ] net-_u75-pad2_ u79 +a58 d3 net-_u75-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u37-pad2_ unconnected-_u75-pad6_ u75 +a59 [net-_u63-pad1_ net-_u63-pad2_ ] net-_u83-pad2_ u87 +a60 d4 net-_u80-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u30-pad2_ unconnected-_u80-pad6_ u80 +a61 [net-_u60-pad1_ net-_u60-pad2_ ] net-_u80-pad2_ u84 +a62 d4 net-_u81-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u34-pad2_ unconnected-_u81-pad6_ u81 +a63 d4 net-_u82-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u40-pad2_ unconnected-_u82-pad6_ u82 +a64 [net-_u62-pad1_ net-_u62-pad2_ ] net-_u82-pad2_ u86 +a65 d4 net-_u83-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u36-pad2_ unconnected-_u83-pad6_ u83 +a66 wb net-_u94-pad2_ u97 +a67 gw_bar net-_u62-pad1_ u93 +a68 [wa net-_u94-pad2_ ] net-_u62-pad2_ u94 +a69 wa net-_u92-pad1_ u96 +a70 [net-_u92-pad1_ wb ] net-_u61-pad2_ u92 +a71 [net-_u61-pad1_ net-_u61-pad2_ ] net-_u81-pad2_ u85 +a72 [wa wb ] net-_u60-pad2_ u90 +a73 gw_bar net-_u60-pad1_ u89 +a74 gw_bar net-_u61-pad1_ u91 +a75 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a76 [net-_u6-pad1_ net-_u10-pad3_ ] q3 u6 +a77 [net-_u21-pad3_ net-_u25-pad3_ ] net-_u6-pad1_ u8 +a78 [net-_u22-pad3_ net-_u16-pad3_ ] net-_u5-pad2_ u9 +a79 [net-_u26-pad3_ net-_u28-pad3_ ] net-_u5-pad1_ u7 +a80 [net-_u5-pad1_ net-_u5-pad2_ ] q2 u5 +a81 [net-_u40-pad1_ net-_u40-pad2_ ] net-_u24-pad2_ u40 +a82 [net-_u14-pad1_ net-_u23-pad2_ ] net-_u23-pad3_ u23 +a83 [net-_u2-pad1_ net-_u2-pad2_ ] q1 u2 +a84 [net-_u23-pad3_ net-_u17-pad3_ ] net-_u2-pad2_ u4 +a85 [net-_u27-pad3_ net-_u29-pad3_ ] net-_u2-pad1_ u3 +a86 [net-_u14-pad1_ net-_u29-pad2_ ] net-_u29-pad3_ u29 +a87 [net-_u14-pad1_ net-_u25-pad2_ ] net-_u25-pad3_ u25 +a88 [net-_u14-pad1_ net-_u28-pad2_ ] net-_u28-pad3_ u28 +a89 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u11-pad1_ u12 +a90 [net-_u11-pad1_ net-_u11-pad2_ ] q4 u11 +a91 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u11-pad2_ u13 +a92 [net-_u14-pad1_ net-_u27-pad2_ ] net-_u27-pad3_ u27 +a93 [net-_u36-pad1_ net-_u42-pad2_ ] net-_u26-pad2_ u42 +a94 [net-_u36-pad1_ net-_u36-pad2_ ] net-_u20-pad2_ u36 +a95 [net-_u36-pad1_ net-_u37-pad2_ ] net-_u21-pad2_ u37 +a96 [net-_u36-pad1_ net-_u43-pad2_ ] net-_u27-pad2_ u43 +a97 [net-_u14-pad1_ net-_u26-pad2_ ] net-_u26-pad3_ u26 +a98 [net-_u14-pad1_ net-_u21-pad2_ ] net-_u21-pad3_ u21 +a99 [net-_u14-pad1_ net-_u20-pad2_ ] net-_u12-pad1_ u20 +* Schematic Name: d_and, Ngspice Name: d_and +.model u50 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u54 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u77 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u78 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u58 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u74 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u66 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u69 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u61 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u57 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u60 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u56 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u49 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u68 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u65 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u73 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u76 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u64 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u72 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u46 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u55 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u52 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u51 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u63 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u67 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u71 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u70 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u59 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u62 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u53 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u48 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u47 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u35 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u39 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u45 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u41 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u44 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u98 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u99 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u95 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u88 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u100 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u79 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u75 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u87 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u80 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u84 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u81 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u82 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u86 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u83 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u97 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u93 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u94 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u96 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u92 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u85 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u90 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u89 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u91 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, Ngspice Name: d_xor +.model u10 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, Ngspice Name: d_xor +.model u6 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, Ngspice Name: d_xor +.model u8 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, Ngspice Name: d_xor +.model u9 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, Ngspice Name: d_xor +.model u7 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, Ngspice Name: d_xor +.model u5 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u40 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, Ngspice Name: d_xor +.model u2 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, Ngspice Name: d_xor +.model u4 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, Ngspice Name: d_xor +.model u3 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, Ngspice Name: d_xor +.model u12 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, Ngspice Name: d_xor +.model u11 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, Ngspice Name: d_xor +.model u13 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u42 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u37 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u43 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN54170/SN54170.kicad_sch b/library/SubcircuitLibrary/SN54170/SN54170.kicad_sch new file mode 100644 index 000000000..2f1c98c3d --- /dev/null +++ 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(footprint "") + ) + (path "/ee2930a0-a317-4760-aec1-81a86fba3d52" + (reference "U67") (unit 1) (value "d_dlatch") (footprint "") + ) + (path "/d63a499e-789b-46d5-a214-ceb6d021d549" + (reference "U68") (unit 1) (value "d_and") (footprint "") + ) + (path "/16fd182c-c378-43a4-9cb8-9942ebb0b382" + (reference "U69") (unit 1) (value "d_and") (footprint "") + ) + (path "/cc028e67-da82-426f-a87d-08565591f8b7" + (reference "U70") (unit 1) (value "d_and") (footprint "") + ) + (path "/635e789b-c69d-4aba-9ce3-ff93a9f433fd" + (reference "U71") (unit 1) (value "d_and") (footprint "") + ) + (path "/976d78b5-4dd9-417d-9daa-569c9b6be03f" + (reference "U72") (unit 1) (value "d_dlatch") (footprint "") + ) + (path "/20640000-cb4b-4fb7-94cf-6e6d10487809" + (reference "U73") (unit 1) (value "d_dlatch") (footprint "") + ) + (path "/b05c0e76-23a9-4eef-b216-9c00f45a0480" + (reference "U74") (unit 1) (value "d_dlatch") (footprint "") + ) + (path "/e104992d-0fa4-403e-9b52-555ad0dcaddb" + (reference "U75") (unit 1) (value "d_dlatch") (footprint "") + ) + (path "/b01831f7-8fe0-4222-8f6c-a67111f77515" + (reference "U76") (unit 1) (value "d_and") (footprint "") + ) + (path "/61a48bad-dd66-4be1-bbc9-a971b66463a7" + (reference "U77") (unit 1) (value "d_and") (footprint "") + ) + (path "/2be38688-05e8-497e-81e1-c0584e918f31" + (reference "U78") (unit 1) (value "d_and") (footprint "") + ) + (path "/bcdbecfe-5d23-4ace-9e54-2ed746ae61dd" + (reference "U79") (unit 1) (value "d_and") (footprint "") + ) + (path "/8ab7db10-d94c-40dd-b5bb-0a710e01880a" + (reference "U80") (unit 1) (value "d_dlatch") (footprint "") + ) + (path "/0308eece-82c4-4894-a5ec-d04bcb4bf5d5" + (reference "U81") (unit 1) (value "d_dlatch") (footprint "") + ) + (path "/8eedbdfc-48d6-4513-95c6-a18bdb71c654" + (reference "U82") (unit 1) (value "d_dlatch") (footprint "") + ) + (path "/3fc75313-b5ef-4f3a-9f90-ecaa8edf497a" + (reference "U83") (unit 1) (value "d_dlatch") (footprint "") + ) + (path "/640fef26-6b78-496d-a74a-4d77cf6503c5" + (reference "U84") (unit 1) (value "d_and") (footprint "") + ) + (path "/55b4fac7-647c-408a-9feb-16bfbb495f6a" + (reference "U85") (unit 1) (value "d_and") (footprint "") + ) + (path "/05395543-3153-4be3-9e27-3365153afaf9" + (reference "U86") (unit 1) (value "d_and") (footprint "") + ) + (path "/2c659b7a-fab2-49ac-8796-57f03a6521ea" + (reference "U87") (unit 1) (value "d_and") (footprint "") + ) + (path "/845eb958-07af-450c-974c-867709f2d521" + (reference "U88") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/5c0062dd-73fd-4a19-a707-f24e31df4a21" + (reference "U89") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/9b612436-b272-4e63-a850-baa9cc8fc2b2" + (reference "U90") (unit 1) (value "d_and") (footprint "") + ) + (path "/5e169d4a-6532-4a0d-ad02-7e8bd5c4c3f2" + (reference "U91") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/7bd25bfc-271c-426f-996e-b9bfdb965e8c" + (reference "U92") (unit 1) (value "d_and") (footprint "") + ) + (path "/1ec8449f-9711-423e-bcf3-e5051fc54c51" + (reference "U93") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/7e9e159e-79ae-4072-a2cb-506b0aaf8748" + (reference "U94") (unit 1) (value "d_and") (footprint "") + ) + (path "/888af7d7-310c-4d3c-ac42-1549215f4790" + (reference "U95") (unit 1) (value "d_and") (footprint "") + ) + (path "/9d8d1de3-8684-4e24-a6f6-45f82fbb99e9" + (reference "U96") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/25f59019-b128-4fb1-b5ba-d96c0d6b25cb" + (reference "U97") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/91e9e946-36b0-4696-bf5a-b02f35481db1" + (reference "U98") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/d47d6362-9a96-47b4-a66a-be6e69203592" + (reference "U99") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/7666efab-89a5-4d9b-8dc2-b28a4daa1e5e" + (reference "U100") (unit 1) (value "adc_bridge_1") (footprint "") + ) + ) +) diff --git a/library/SubcircuitLibrary/SN54170/SN54170.sub b/library/SubcircuitLibrary/SN54170/SN54170.sub new file mode 100644 index 000000000..8ec349bfb --- /dev/null +++ b/library/SubcircuitLibrary/SN54170/SN54170.sub @@ -0,0 +1,402 @@ +* Subcircuit SN54170 +.subckt SN54170 d2 d3 d4 rb ra q4 q3 gnd q2 q1 gr_bar gw_bar wb wa d1 unconnected-_u1-pad16_ +.title kicad schematic +* u50 net-_u50-pad1_ rb net-_u34-pad1_ d_and +* u54 ra net-_u50-pad1_ d_inverter +* u77 net-_u61-pad1_ net-_u61-pad2_ net-_u73-pad2_ d_and +* u78 net-_u62-pad1_ net-_u62-pad2_ net-_u74-pad2_ d_and +* u58 d1 net-_u58-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u45-pad2_ unconnected-_u58-pad6_ d_dlatch +* u74 d3 net-_u74-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u41-pad2_ unconnected-_u74-pad6_ d_dlatch +* u66 d2 net-_u66-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u44-pad2_ unconnected-_u66-pad6_ d_dlatch +* u69 net-_u61-pad1_ net-_u61-pad2_ net-_u65-pad2_ d_and +* u61 net-_u61-pad1_ net-_u61-pad2_ net-_u57-pad2_ d_and +* u57 d1 net-_u57-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u39-pad2_ unconnected-_u57-pad6_ d_dlatch +* u60 net-_u60-pad1_ net-_u60-pad2_ net-_u56-pad2_ d_and +* u56 d1 net-_u56-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u33-pad2_ unconnected-_u56-pad6_ d_dlatch +* u49 ra rb net-_u30-pad1_ d_and +* u68 net-_u60-pad1_ net-_u60-pad2_ net-_u64-pad2_ d_and +* u65 d2 net-_u65-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u38-pad2_ unconnected-_u65-pad6_ d_dlatch +* u73 d3 net-_u73-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u35-pad2_ unconnected-_u73-pad6_ d_dlatch +* u76 net-_u60-pad1_ net-_u60-pad2_ net-_u72-pad2_ d_and +* u64 d2 net-_u64-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u32-pad2_ unconnected-_u64-pad6_ d_dlatch +* u72 d3 net-_u72-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u31-pad2_ unconnected-_u72-pad6_ d_dlatch +* u46 gr_bar net-_u14-pad1_ d_inverter +* u55 gnd net-_u55-pad2_ adc_bridge_1 +* u52 rb net-_u47-pad2_ d_inverter +* u51 ra net-_u47-pad1_ d_inverter +* u63 net-_u63-pad1_ net-_u63-pad2_ net-_u59-pad2_ d_and +* u67 d2 net-_u67-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u42-pad2_ unconnected-_u67-pad6_ d_dlatch +* u71 net-_u63-pad1_ net-_u63-pad2_ net-_u67-pad2_ d_and +* u70 net-_u62-pad1_ net-_u62-pad2_ net-_u66-pad2_ d_and +* u59 d1 net-_u59-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u43-pad2_ unconnected-_u59-pad6_ d_dlatch +* u62 net-_u62-pad1_ net-_u62-pad2_ net-_u58-pad2_ d_and +* u53 rb net-_u48-pad2_ d_inverter +* u48 ra net-_u48-pad2_ net-_u40-pad1_ d_and +* u47 net-_u47-pad1_ net-_u47-pad2_ net-_u36-pad1_ d_and +* u22 net-_u14-pad1_ net-_u22-pad2_ net-_u22-pad3_ d_and +* u35 net-_u34-pad1_ net-_u35-pad2_ net-_u19-pad2_ d_and +* u34 net-_u34-pad1_ net-_u34-pad2_ net-_u18-pad2_ d_and +* u18 net-_u14-pad1_ net-_u18-pad2_ net-_u13-pad1_ d_and +* u19 net-_u14-pad1_ net-_u19-pad2_ net-_u10-pad1_ d_and +* u39 net-_u34-pad1_ net-_u39-pad2_ net-_u23-pad2_ d_and +* u38 net-_u34-pad1_ net-_u38-pad2_ net-_u22-pad2_ d_and +* u33 net-_u30-pad1_ net-_u33-pad2_ net-_u17-pad2_ d_and +* u30 net-_u30-pad1_ net-_u30-pad2_ net-_u14-pad2_ d_and +* u15 net-_u14-pad1_ net-_u15-pad2_ net-_u10-pad2_ d_and +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u13-pad2_ d_and +* u31 net-_u30-pad1_ net-_u31-pad2_ net-_u15-pad2_ d_and +* u32 net-_u30-pad1_ net-_u32-pad2_ net-_u16-pad2_ d_and +* u17 net-_u14-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_and +* u16 net-_u14-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_and +* u45 net-_u40-pad1_ net-_u45-pad2_ net-_u29-pad2_ d_and +* u24 net-_u14-pad1_ net-_u24-pad2_ net-_u12-pad2_ d_and +* u41 net-_u40-pad1_ net-_u41-pad2_ net-_u25-pad2_ d_and +* u44 net-_u40-pad1_ net-_u44-pad2_ net-_u28-pad2_ d_and +* u98 wa net-_u95-pad1_ d_inverter +* u99 wb net-_u95-pad2_ d_inverter +* u95 net-_u95-pad1_ net-_u95-pad2_ net-_u63-pad2_ d_and +* u88 gw_bar net-_u63-pad1_ d_inverter +* u100 gnd net-_u100-pad2_ adc_bridge_1 +* u79 net-_u63-pad1_ net-_u63-pad2_ net-_u75-pad2_ d_and +* u75 d3 net-_u75-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u37-pad2_ unconnected-_u75-pad6_ d_dlatch +* u87 net-_u63-pad1_ net-_u63-pad2_ net-_u83-pad2_ d_and +* u80 d4 net-_u80-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u30-pad2_ unconnected-_u80-pad6_ d_dlatch +* u84 net-_u60-pad1_ net-_u60-pad2_ net-_u80-pad2_ d_and +* u81 d4 net-_u81-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u34-pad2_ unconnected-_u81-pad6_ d_dlatch +* u82 d4 net-_u82-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u40-pad2_ unconnected-_u82-pad6_ d_dlatch +* u86 net-_u62-pad1_ net-_u62-pad2_ net-_u82-pad2_ d_and +* u83 d4 net-_u83-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u36-pad2_ unconnected-_u83-pad6_ d_dlatch +* u97 wb net-_u94-pad2_ d_inverter +* u93 gw_bar net-_u62-pad1_ d_inverter +* u94 wa net-_u94-pad2_ net-_u62-pad2_ d_and +* u96 wa net-_u92-pad1_ d_inverter +* u92 net-_u92-pad1_ wb net-_u61-pad2_ d_and +* u85 net-_u61-pad1_ net-_u61-pad2_ net-_u81-pad2_ d_and +* u90 wa wb net-_u60-pad2_ d_and +* u89 gw_bar net-_u60-pad1_ d_inverter +* u91 gw_bar net-_u61-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_xor +* u6 net-_u6-pad1_ net-_u10-pad3_ q3 d_xor +* u8 net-_u21-pad3_ net-_u25-pad3_ net-_u6-pad1_ d_xor +* u9 net-_u22-pad3_ net-_u16-pad3_ net-_u5-pad2_ d_xor +* u7 net-_u26-pad3_ net-_u28-pad3_ net-_u5-pad1_ d_xor +* u5 net-_u5-pad1_ net-_u5-pad2_ q2 d_xor +* u40 net-_u40-pad1_ net-_u40-pad2_ net-_u24-pad2_ d_and +* u23 net-_u14-pad1_ net-_u23-pad2_ net-_u23-pad3_ d_and +* u2 net-_u2-pad1_ net-_u2-pad2_ q1 d_xor +* u4 net-_u23-pad3_ net-_u17-pad3_ net-_u2-pad2_ d_xor +* u3 net-_u27-pad3_ net-_u29-pad3_ net-_u2-pad1_ d_xor +* u29 net-_u14-pad1_ net-_u29-pad2_ net-_u29-pad3_ d_and +* u25 net-_u14-pad1_ net-_u25-pad2_ net-_u25-pad3_ d_and +* u28 net-_u14-pad1_ net-_u28-pad2_ net-_u28-pad3_ d_and +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u11-pad1_ d_xor +* u11 net-_u11-pad1_ net-_u11-pad2_ q4 d_xor +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u11-pad2_ d_xor +* u27 net-_u14-pad1_ net-_u27-pad2_ net-_u27-pad3_ d_and +* u42 net-_u36-pad1_ net-_u42-pad2_ net-_u26-pad2_ d_and +* u36 net-_u36-pad1_ net-_u36-pad2_ net-_u20-pad2_ d_and +* u37 net-_u36-pad1_ net-_u37-pad2_ net-_u21-pad2_ d_and +* u43 net-_u36-pad1_ net-_u43-pad2_ net-_u27-pad2_ d_and +* u26 net-_u14-pad1_ net-_u26-pad2_ net-_u26-pad3_ d_and +* u21 net-_u14-pad1_ net-_u21-pad2_ net-_u21-pad3_ d_and +* u20 net-_u14-pad1_ net-_u20-pad2_ net-_u12-pad1_ d_and +a1 [net-_u50-pad1_ rb ] net-_u34-pad1_ u50 +a2 ra net-_u50-pad1_ u54 +a3 [net-_u61-pad1_ net-_u61-pad2_ ] net-_u73-pad2_ u77 +a4 [net-_u62-pad1_ net-_u62-pad2_ ] net-_u74-pad2_ u78 +a5 d1 net-_u58-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u45-pad2_ unconnected-_u58-pad6_ u58 +a6 d3 net-_u74-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u41-pad2_ unconnected-_u74-pad6_ u74 +a7 d2 net-_u66-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u44-pad2_ unconnected-_u66-pad6_ u66 +a8 [net-_u61-pad1_ net-_u61-pad2_ ] net-_u65-pad2_ u69 +a9 [net-_u61-pad1_ net-_u61-pad2_ ] net-_u57-pad2_ u61 +a10 d1 net-_u57-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u39-pad2_ unconnected-_u57-pad6_ u57 +a11 [net-_u60-pad1_ net-_u60-pad2_ ] net-_u56-pad2_ u60 +a12 d1 net-_u56-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u33-pad2_ unconnected-_u56-pad6_ u56 +a13 [ra rb ] net-_u30-pad1_ u49 +a14 [net-_u60-pad1_ net-_u60-pad2_ ] net-_u64-pad2_ u68 +a15 d2 net-_u65-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u38-pad2_ unconnected-_u65-pad6_ u65 +a16 d3 net-_u73-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u35-pad2_ unconnected-_u73-pad6_ u73 +a17 [net-_u60-pad1_ net-_u60-pad2_ ] net-_u72-pad2_ u76 +a18 d2 net-_u64-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u32-pad2_ unconnected-_u64-pad6_ u64 +a19 d3 net-_u72-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u31-pad2_ unconnected-_u72-pad6_ u72 +a20 gr_bar net-_u14-pad1_ u46 +a21 [gnd ] [net-_u55-pad2_ ] u55 +a22 rb net-_u47-pad2_ u52 +a23 ra net-_u47-pad1_ u51 +a24 [net-_u63-pad1_ net-_u63-pad2_ ] net-_u59-pad2_ u63 +a25 d2 net-_u67-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u42-pad2_ unconnected-_u67-pad6_ u67 +a26 [net-_u63-pad1_ net-_u63-pad2_ ] net-_u67-pad2_ u71 +a27 [net-_u62-pad1_ net-_u62-pad2_ ] net-_u66-pad2_ u70 +a28 d1 net-_u59-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u43-pad2_ unconnected-_u59-pad6_ u59 +a29 [net-_u62-pad1_ net-_u62-pad2_ ] net-_u58-pad2_ u62 +a30 rb net-_u48-pad2_ u53 +a31 [ra net-_u48-pad2_ ] net-_u40-pad1_ u48 +a32 [net-_u47-pad1_ net-_u47-pad2_ ] net-_u36-pad1_ u47 +a33 [net-_u14-pad1_ net-_u22-pad2_ ] net-_u22-pad3_ u22 +a34 [net-_u34-pad1_ net-_u35-pad2_ ] net-_u19-pad2_ u35 +a35 [net-_u34-pad1_ net-_u34-pad2_ ] net-_u18-pad2_ u34 +a36 [net-_u14-pad1_ net-_u18-pad2_ ] net-_u13-pad1_ u18 +a37 [net-_u14-pad1_ net-_u19-pad2_ ] net-_u10-pad1_ u19 +a38 [net-_u34-pad1_ net-_u39-pad2_ ] net-_u23-pad2_ u39 +a39 [net-_u34-pad1_ net-_u38-pad2_ ] net-_u22-pad2_ u38 +a40 [net-_u30-pad1_ net-_u33-pad2_ ] net-_u17-pad2_ u33 +a41 [net-_u30-pad1_ net-_u30-pad2_ ] net-_u14-pad2_ u30 +a42 [net-_u14-pad1_ net-_u15-pad2_ ] net-_u10-pad2_ u15 +a43 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u13-pad2_ u14 +a44 [net-_u30-pad1_ net-_u31-pad2_ ] net-_u15-pad2_ u31 +a45 [net-_u30-pad1_ net-_u32-pad2_ ] net-_u16-pad2_ u32 +a46 [net-_u14-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17 +a47 [net-_u14-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16 +a48 [net-_u40-pad1_ net-_u45-pad2_ ] net-_u29-pad2_ u45 +a49 [net-_u14-pad1_ net-_u24-pad2_ ] net-_u12-pad2_ u24 +a50 [net-_u40-pad1_ net-_u41-pad2_ ] net-_u25-pad2_ u41 +a51 [net-_u40-pad1_ net-_u44-pad2_ ] net-_u28-pad2_ u44 +a52 wa net-_u95-pad1_ u98 +a53 wb net-_u95-pad2_ u99 +a54 [net-_u95-pad1_ net-_u95-pad2_ ] net-_u63-pad2_ u95 +a55 gw_bar net-_u63-pad1_ u88 +a56 [gnd ] [net-_u100-pad2_ ] u100 +a57 [net-_u63-pad1_ net-_u63-pad2_ ] net-_u75-pad2_ u79 +a58 d3 net-_u75-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u37-pad2_ unconnected-_u75-pad6_ u75 +a59 [net-_u63-pad1_ net-_u63-pad2_ ] net-_u83-pad2_ u87 +a60 d4 net-_u80-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u30-pad2_ unconnected-_u80-pad6_ u80 +a61 [net-_u60-pad1_ net-_u60-pad2_ ] net-_u80-pad2_ u84 +a62 d4 net-_u81-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u34-pad2_ unconnected-_u81-pad6_ u81 +a63 d4 net-_u82-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u40-pad2_ unconnected-_u82-pad6_ u82 +a64 [net-_u62-pad1_ net-_u62-pad2_ ] net-_u82-pad2_ u86 +a65 d4 net-_u83-pad2_ net-_u55-pad2_ net-_u100-pad2_ net-_u36-pad2_ unconnected-_u83-pad6_ u83 +a66 wb net-_u94-pad2_ u97 +a67 gw_bar net-_u62-pad1_ u93 +a68 [wa net-_u94-pad2_ ] net-_u62-pad2_ u94 +a69 wa net-_u92-pad1_ u96 +a70 [net-_u92-pad1_ wb ] net-_u61-pad2_ u92 +a71 [net-_u61-pad1_ net-_u61-pad2_ ] net-_u81-pad2_ u85 +a72 [wa wb ] net-_u60-pad2_ u90 +a73 gw_bar net-_u60-pad1_ u89 +a74 gw_bar net-_u61-pad1_ u91 +a75 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a76 [net-_u6-pad1_ net-_u10-pad3_ ] q3 u6 +a77 [net-_u21-pad3_ net-_u25-pad3_ ] net-_u6-pad1_ u8 +a78 [net-_u22-pad3_ net-_u16-pad3_ ] net-_u5-pad2_ u9 +a79 [net-_u26-pad3_ net-_u28-pad3_ ] net-_u5-pad1_ u7 +a80 [net-_u5-pad1_ net-_u5-pad2_ ] q2 u5 +a81 [net-_u40-pad1_ net-_u40-pad2_ ] net-_u24-pad2_ u40 +a82 [net-_u14-pad1_ net-_u23-pad2_ ] net-_u23-pad3_ u23 +a83 [net-_u2-pad1_ net-_u2-pad2_ ] q1 u2 +a84 [net-_u23-pad3_ net-_u17-pad3_ ] net-_u2-pad2_ u4 +a85 [net-_u27-pad3_ net-_u29-pad3_ ] net-_u2-pad1_ u3 +a86 [net-_u14-pad1_ net-_u29-pad2_ ] net-_u29-pad3_ u29 +a87 [net-_u14-pad1_ net-_u25-pad2_ ] net-_u25-pad3_ u25 +a88 [net-_u14-pad1_ net-_u28-pad2_ ] net-_u28-pad3_ u28 +a89 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u11-pad1_ u12 +a90 [net-_u11-pad1_ net-_u11-pad2_ ] q4 u11 +a91 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u11-pad2_ u13 +a92 [net-_u14-pad1_ net-_u27-pad2_ ] net-_u27-pad3_ u27 +a93 [net-_u36-pad1_ net-_u42-pad2_ ] net-_u26-pad2_ u42 +a94 [net-_u36-pad1_ net-_u36-pad2_ ] net-_u20-pad2_ u36 +a95 [net-_u36-pad1_ net-_u37-pad2_ ] net-_u21-pad2_ u37 +a96 [net-_u36-pad1_ net-_u43-pad2_ ] net-_u27-pad2_ u43 +a97 [net-_u14-pad1_ net-_u26-pad2_ ] net-_u26-pad3_ u26 +a98 [net-_u14-pad1_ net-_u21-pad2_ ] net-_u21-pad3_ u21 +a99 [net-_u14-pad1_ net-_u20-pad2_ ] net-_u12-pad1_ u20 +* Schematic Name: d_and, Ngspice Name: d_and +.model u50 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u54 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u77 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u78 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u58 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u74 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u66 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u69 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u61 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u57 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u60 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u56 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u49 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u68 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u65 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u73 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u76 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u64 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u72 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u46 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u55 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u52 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u51 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u63 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u67 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u71 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u70 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u59 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u62 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u53 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u48 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u47 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u35 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u39 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u45 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u41 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u44 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u98 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u99 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u95 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u88 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, Ngspice Name: adc_bridge +.model u100 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u79 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u75 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u87 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u80 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u84 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u81 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u82 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u86 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dlatch, Ngspice Name: d_dlatch +.model u83 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u97 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u93 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u94 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u96 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u92 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u85 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u90 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u89 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u91 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, Ngspice Name: d_xor +.model u10 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, Ngspice Name: d_xor +.model u6 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, Ngspice Name: d_xor +.model u8 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, Ngspice Name: d_xor +.model u9 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, Ngspice Name: d_xor +.model u7 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, Ngspice Name: d_xor +.model u5 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u40 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, Ngspice Name: d_xor +.model u2 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, Ngspice Name: d_xor +.model u4 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, Ngspice Name: d_xor +.model u3 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, Ngspice Name: d_xor +.model u12 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, Ngspice Name: d_xor +.model u11 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, Ngspice Name: d_xor +.model u13 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u42 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u37 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u43 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, Ngspice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SN54170 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54170/SN54170_Previous_Values.xml b/library/SubcircuitLibrary/SN54170/SN54170_Previous_Values.xml new file mode 100644 index 000000000..46efe220a --- /dev/null +++ b/library/SubcircuitLibrary/SN54170/SN54170_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_andd_inverterd_andd_andd_dlatchd_dlatchd_dlatchd_andd_andd_dlatchd_andd_dlatchd_andd_andd_dlatchd_dlatchd_andd_dlatchd_dlatchd_inverteradc_bridged_inverterd_inverterd_andd_dlatchd_andd_andd_dlatchd_andd_inverterd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_inverterd_inverterd_andd_inverteradc_bridged_andd_dlatchd_andd_dlatchd_andd_dlatchd_dlatchd_andd_dlatchd_inverterd_inverterd_andd_inverterd_andd_andd_andd_inverterd_inverterd_xord_xord_xord_xord_xord_xord_andd_andd_xord_xord_xord_andd_andd_andd_xord_xord_xord_andd_andd_andd_andd_andd_andd_andd_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54170/analysis b/library/SubcircuitLibrary/SN54170/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/SN54170/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file